<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/125950>125950</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            AMDGPU: can optimize away v_readfirstlane_b32 on implicit_def input
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          rampitec
      </td>
    </tr>
</table>

<pre>
    For the small testcase:
```
; RUN: llc -march=amdgcn -mcpu=gfx900 < %s

; Only one readfistlane is really needed

define amdgpu_ps void @test(i32 %in, ptr %out) {
  %v1 = insertelement <2 x i32> <i32 poison, i32 poison>, i32 %in, i32 0
  %v2 = bitcast <2 x i32> %v1 to i64
  %v3 = call i64 @llvm.amdgcn.s.quadmask.i64(i64 %v2)
  %p = inttoptr i64 %v2 to ptr addrspace(4)
  store i64 %v3, ptr %out
  ret void
}
```

We are producing code which has 2 v_readfirstlane_b32 instructions. Only one is needed as second one reads undef:

```
        v_readfirstlane_b32 s0, v0
        v_readfirstlane_b32 s1, v1
        s_quadmask_b64 s[0:1], s[0:1]
        v_mov_b32_e32 v4, s1
        v_mov_b32_e32 v3, s0
 flat_store_dwordx2 v[1:2], v[3:4]
        s_endpgm
```
Although backend does not see it is undef behind the REG_SEQUENCE.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJyEVE1v4zYQ_TX0ZRCDIiXLPuggx_aeum23CHoUKHJksUuRKkkpSX99QfljkzTFGgaEId68N_NmSBGCPlvEihR7UhxWYoq985UXw6gjylXr1Gt1ch5ijxAGYQxEDFGKgITXhNZkQ69_WhO-h29PXwmvwRgJD4Pwsif8IAZ1lhYeBjlOhB_O3cuOUiD8EQgrQkq85P5qzSs4i-BRqE6HaIRF0CHFxryCRVSoLniFnbYIiXqcmjHA7LQCktNUHmFbzVli15awRxijT4GbImE7IOWe0BrSyZwB4QfQNqCPaHBAG1NhDF5Ac0b4MUWJa3Q6uIXsTcSPt4O7VAronZ4t9K1Ohv2HeJGPDvQmvyfwJUEmn_UmT_0YMw_ri4PrsP57EmoQ4fs6JbHtgkk6hO1uHOO1pRhd6vsOSVLpQCjlwygkErbNb3khOo93LP9gWkJ4jIvHyf7y8HHytP4TQXiE0Ts1SW3PIJ1CeO617KEXARjMzWWu_jLYpuUsOR_9JKN2Nqx_LIAO12GDCBBQOqvuixFgsgq76_q9rwOuv8-kAk1dzT-FZQssewMLzc32pt3kEEixp4TXGSkOCfsufks-uDlRNsgZzPkCzf4fsJgelvI6I2KzjKRRz86rFwYzKfYZ4TW7iqaYE17n70VDg1aN5-GDL7WJvZvOPbRCfkerQDkMYF2EgAg6JsMXV6HFXlu1XPdvxy_NH8ffn45fH4_rlaq42vGdWGGVlXxb7vKyKFd91SLNy23bdnm3kSXrOiw47nJRoMrLjONKV4yygjJaMMYZL9e7kndbRkuU3abdbDKSUxyENutl1Z0_r3QIE1YZK3YFXRnRogm3B8pXCfXQTueQLocOMfzIizoarOpfDl9-e0qvkBQW3Bj1oP9BEM_i9dOJOwt6GI2WOjbJAm3HKa4mb6o-xjGkRWMnwk5nHfupXUs3EHZKmtfPw-jdXygjYael8EDY6Vr7XLF_AwAA__96WJzo">