<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/124023>124023</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [LLDB] RISC-V has missing aliases for registers
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          patryk4815
      </td>
    </tr>
</table>

<pre>
    Same issue as in https://github.com/llvm/llvm-project/issues/123903
When debugging with qemu-riscv64, some registers lack their standard aliases.

How to reproduce
```
(lldb) target create -p qemu-user ./result/bin/hello
(lldb) settings set platform.plugin.qemu-user.architecture riscv64
(lldb) b main
(lldb) run
(lldb) register read $x0
```

```
(lldb) register read x0
zero = 0x0000000000000000
(lldb) register read x1
ra = 0x0000ffffa6ca08c0 
(lldb) register read x2
sp = 0x0000ffffa760b7f0
(lldb) register read x3
gp = 0x000000000001a800
(lldb) register read x3
gp = 0x000000000001a800
(lldb) register read x4
error: Invalid register name 'x4'.
(lldb) register read x5
error: Invalid register name 'x5'.
(lldb) register read x6
error: Invalid register name 'x6'.
(lldb) register read x7
error: Invalid register name 'x7'.
....
```

```
python3          < 49> send packet: $qXfer:features:read:riscv-64bit-cpu.xml:0,fff#68
python3 <   1> read packet: +
python3          <1829> read packet: $l<?xml version="1.0"?>
<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.

     Copying and distribution of this file, with or without modification,
     are permitted in any medium without royalty provided the copyright
     notice and this notice are preserved.  -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.cpu">
  <reg name="zero" bitsize="64" type="int"/>
  <reg name="ra" bitsize="64" type="code_ptr"/>
  <reg name="sp" bitsize="64" type="data_ptr"/>
  <reg name="gp" bitsize="64" type="data_ptr"/>
  <reg name="tp" bitsize="64" type="data_ptr"/>
  <reg name="t0" bitsize="64" type="int"/>
  <reg name="t1" bitsize="64" type="int"/>
  <reg name="t2" bitsize="64" type="int"/>
  <reg name="fp" bitsize="64" type="data_ptr"/>
  <reg name="s1" bitsize="64" type="int"/>
  <reg name="a0" bitsize="64" type="int"/>
  <reg name="a1" bitsize="64" type="int"/>
  <reg name="a2" bitsize="64" type="int"/>
  <reg name="a3" bitsize="64" type="int"/>
  <reg name="a4" bitsize="64" type="int"/>
  <reg name="a5" bitsize="64" type="int"/>
  <reg name="a6" bitsize="64" type="int"/>
  <reg name="a7" bitsize="64" type="int"/>
  <reg name="s2" bitsize="64" type="int"/>
  <reg name="s3" bitsize="64" type="int"/>
  <reg name="s4" bitsize="64" type="int"/>
  <reg name="s5" bitsize="64" type="int"/>
  <reg name="s6" bitsize="64" type="int"/>
  <reg name="s7" bitsize="64" type="int"/>
  <reg name="s8" bitsize="64" type="int"/>
  <reg name="s9" bitsize="64" type="int"/>
  <reg name="s10" bitsize="64" type="int"/>
  <reg name="s11" bitsize="64" type="int"/>
  <reg name="t3" bitsize="64" type="int"/>
  <reg name="t4" bitsize="64" type="int"/>
  <reg name="t5" bitsize="64" type="int"/>
  <reg name="t6" bitsize="64" type="int"/>
  <reg name="pc" bitsize="64" type="code_ptr"/>
</feature>
```
</pre>

<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJysmN9v2zYQx_8a-uVggTrKtvzgB9eJsAIdNizFtj4NlHiSuEqiSlJO3L9-oGKnSbYmQUcjgGJC38_91JmidE43A9GOrd6x1dVCTr41djdKb0-fszxdLUqjTrsb2RNo5yYC6UAP0Ho_Oib2DAuGRaN9O5VJZXqGRdcdL5flaM3fVHmGxSx2DIsUxZYLxvd_tDSAonJqGj00cKt9C1-on5ZWu-q4zhgewJmewFKjnSfroJPVZ_AtaQvOy0FJq0B2WjpyCeN7xvc_mVvwBiyN1qiporC65uc_vmeYd50qGW7BS9uQh8qS9ATL8d725MhCwrCw5KYuOF7qgWHRUteZpwBH3uuhceEfGDvpa2P7ZOymRg_JAyyRtmq1p8pPluAS2hNQCb3Uw9M1Oz1fOCcBLEkFDLM7_jy274b6VDsLv5I1wMQV8Dv-7POiNmV8b-UjZV3XtVxXkucVhxelyPjejc-lmzUvN_XLRkO3NOO_3U1l_oq7P64MNSJrjWViD--Ho-y0-nbPEJ4Hhpu7jOEmeRG0ehto9Spo_TbQ-lXQ5m2gzRmUJEnycquNJ9-aQcDDh4kDZFsmrsHRoGCU1WfywRrD7MufNQXLNcnwSIQhEtwKl_BwLNdZqf2yGqfkru-Y2HOGh7quGYp1_shWMAGQBhtzVI9tvPuOT2mO2_8UZB0TByaKu76DI1mnzcDEFUNME84QmSiYuA5BiwPDdLmEgxlPVjetB4b5IeQYeZovkadbKCwR3Jja30pLUJhpUNIHIh7g_VCdB9XsU8CE2ScHBUo7b3U5hVvB1OBb7aDWHQXdPByNna9m8tAbpWtdXbgXXjA4ku2196TCmJbDCXpSeuofpNacZOdPMFpz1IpUmKdQXeK5kAbjdUWzY7Mjl-_BgCVH9kgqAVguz4m55Obql8PHT79ew7m6cPPp5uP1z8AQG1Uu72duoryas3pO6eXe0Hn3aTe2SZphShpVJnNXJNU4PUjmWlpqHgnCOGOIUGrv9NfzYvgJQfCn8fxdDz4wsPguxspXIZVR9Nfo7SskN75KUtLLN5CaaCQfj8QjJNunMSAYAVJHS4yLEZOMkV0ZxZMY2ZUiBiSLAVnFgKxjQDYRIC5GdVyM6rgY1XExquNiVMdFqU4eA7KNAUljDBSXRpnXMdrNx2g3H6PdfIx2G6sf2nXMG67ivHk6L1025Qu1E2ortnJBu3QjNqs8T_Ns0e4oI5FXW-JpKsUaqzoVotxWSoh1pVCKhd4hxxVPEVGg4FmSq0wKLNNtWa83PF2xjFMvdZeEF_zE2GYxv9rvUsw4ikUnS-rcfJyAONDt_alB8Ht1tbC7-VSgnBrHMt5p5903jNe-m88hPny4esdWV_Db-5vD8ndopYNeOzdvlO9f9qE29tuxwGKy3e7_HEjMjh93-E8AAAD__yoM3nE">