<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/123375>123375</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [mlir] BlockEquivalenceData is wrong?
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            mlir
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            jpienaar
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          makslevental
      </td>
    </tr>
</table>

<pre>
    ```mlir
 tt.func @condBranch(%arg0: !tt.ptr<f32>, %arg1: i1) -> tensor<1024xf32> {
 %c1024_i32 = arith.constant 1024 : i32
    %0 = tt.get_program_id x : i32
    %1 = arith.muli %0, %c1024_i32 : i32
    %2 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32>
    %3 = tt.splat %1 : i32 -> tensor<1024xi32>
    %4 = arith.addi %3, %2 : tensor<1024xi32>
    %5 = tt.splat %arg0 : !tt.ptr<f32> -> tensor<1024x!tt.ptr<f32>>
    %6 = tt.addptr %5, %4 : tensor<1024x!tt.ptr<f32>>, tensor<1024xi32>
 cf.cond_br %arg1, ^bb1(%5 : tensor<1024x!tt.ptr<f32>>), ^bb2(%6 : tensor<1024x!tt.ptr<f32>>)
  ^bb1(%7: tensor<1024x!tt.ptr<f32>>):  // pred: ^bb0
    %8 = tt.load %7 : tensor<1024x!tt.ptr<f32>>
    tt.return %8 : tensor<1024xf32>
  ^bb2(%9: tensor<1024x!tt.ptr<f32>>):  // pred: ^bb0
 %10 = tt.load %9 : tensor<1024x!tt.ptr<f32>>
    tt.return %10 : tensor<1024xf32>
  }
```

`mlir::simplifyRegions` gives

```mlir
 tt.func @condBranch(%arg0: !tt.ptr<f32>, %arg1: i1) -> tensor<1024xf32> {
 %c0_i64 = arith.constant 0 : i64
    %0 = builtin.unrealized_conversion_cast %arg0, %c0_i64 : !tt.ptr<f32>, i64 to !tt.ptr<f32>
    %c1024_i32 = arith.constant 1024 : i32
    %1 = tt.get_program_id x : i32
    %2 = arith.muli %1, %c1024_i32 : i32
    %3 = tt.make_range {end = 1024 : i32, start = 0 : i32} : tensor<1024xi32>
    %4 = tt.splat %2 : i32 -> tensor<1024xi32>
    %5 = arith.addi %4, %3 : tensor<1024xi32>
    %6 = tt.splat %0 : !tt.ptr<f32> -> tensor<1024x!tt.ptr<f32>>
    %7 = tt.addptr %6, %5 : tensor<1024x!tt.ptr<f32>>, tensor<1024xi32>
    cf.cond_br %arg1, ^bb1(%6 : tensor<1024x!tt.ptr<f32>>), ^bb1(%7 : tensor<1024x!tt.ptr<f32>>)
  ^bb1(%8: tensor<1024x!tt.ptr<f32>>):  // 2 preds: ^bb0, ^bb0
    %9 = tt.load %8 : tensor<1024x!tt.ptr<f32>>
    tt.return %9 : tensor<1024xf32>
 }
```

[because](https://github.com/llvm/llvm-project/blob/1e5f32e81f96af45551dafb369279c6d55ac9b97/mlir/lib/Transforms/Utils/RegionUtils.cpp#L491-L495)

> /// This class contains the information for comparing the equivalencies of two
> /// blocks. Blocks are considered equivalent if they contain the same operations
> /// in the same order. The only allowed divergence is for operands that come
> /// from sources outside of the parent block, i.e. the uses of values produced
> /// within the block must be equivalent.

I don't understand how that's a legal merge/rewrite/change? 


</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzEl12P2ygXxz8NuUG1bPBLfJGLmclEeqRePepeRxiObVoMXsCZzn76FTjJpIlHzXSrXSmSX-D8z__A4ReZOSc7DbBBxSMi5OsoQTNmESGo2K7Y5HtjNwP75hQcQHumVo0RrxtUpvNvUNKi9AF7n7ST5hjlKTdaPFqmeY_IGpGC2S5F9AEjknmfjN4i-tRSgugzIk94npCFCTJDpMafEH3GHrQzYWKWkvz7PBuj6jGkQqTg4fVeUoIR3WJmpe8TbrTzTHscxnDUoyTMxziEpHGq90kHfj9a01k27KXA32-nZheqw6RkDD96vcx8FUZOGQb2DfaW6Q6CZdAiDvxgizxh55n1cSQ9v6628fbH6uW8Vuc89JTHjYr5k-EosLR41-H5RXVMiFgdPVZH7khf3KQPG4yXd3jJ0EIfXOqXJ30mxOhtTHm0ly_YW1YjT-9WwdvQKmLf2HPvBfXiuWmyuWGL-9PU51gyx5YfiQ01XyauPhBLQyzZIbLDowURlz9IpW8ruT6tpDJMhBfV3eZmDe8TC36y-qR2Hdy-9cblItS_q47Q2-l1FfU_qSJLf1JGtUXpwxlv4T4-Rs7RB0QfnBxGJdvX_0MnjXaoTHEnD-DOU_9TMKZ7WeZLVDxCpsyvkdhMUnmpk0lbYEr-BWLPjT6AddLoPWfufMZPCDzleM95GPVmafCc-hcAnt0PcLIA8OznAKf_EsDzG4KSjwC8WAB4fqyO3pG-vEn_G-ld3dK7PHr7AFbfpzfGdwD8QxC-ir2fkQsAX_8a-EhEn7tg38nUBc3raw4uAfluDi5B9O2QLlOweGyAs8kBKraIrHvvx-B5LqKTvp-ahJsBkZ1Sh9Pl02jNV-AekV2jTIPILoOipQTWWVuXrM2LosgEaxta1qSqeSmKgvG6qStEdhGiZKdkiPtimXatsYNDZPeHlypcZwrHp4SPIyL0c15nnz7ndTFvUPgFREaTYbG_9NJhrphzmBvtmdQO-x6w1EGbeWk0bo3F3Awjs1J3cRT-nOSBKdBcgsOmxf7F3Eg3yvBvLsGP8YqZhZDCSQEWxJuEx7INoq8nAzGDYwNgM4KNFtyN-A_TrACb4C89YKPVK2ZKmRcQWMgD2A40ByxdrCIKahFKZD7UBDfCrTUDdmayPFQ2-eA3VtgDHpkNfmNhEe0JJHFgcvMyHJiawOHRGjFxEDfiL9L3R-dRBA-T87i5WFCfzLv0PyyMRqTyeNICbPgrELg3L9E5IpXDDCvomMJDqBGRnYUXK324432ANaI7PGutxIaKmtZsBZusolVG6bqqVv2mSouqWDeUiTXQum3ytizTdVbWrGKFKGAlNyQlRZplVVZlWVYlnHBe8pKUtCG1yGuUpzAwqZLQ3Imx3Uo6N8EmI5RWxUqxBpQ7fk3N7Ru_pOwmHoZm6hzKUyWdd28KXnoVv8BiQLGdG-j53HKwZZ6FHX2xRneI7laTVZsPn79oNByao9fDhvwdAAD__wbH6P0">