<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/123029>123029</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Assert triggered in AArch64ISelLowering::targetShrinkDemandedConstant when using half precision
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          WillFroom
      </td>
    </tr>
</table>

<pre>
    I am emitting machine code using half precision for arm but I am hitting the following [assert](/github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L2376): 
```cpp
assert((Size == 32 || Size == 64) &&
         "i32 or i64 is expected after legalization.");
```

I have create a reproducible example: https://godbolt.org/z/d5aa5cxrK

I think it is possible that the assert is wrong, I believe it may just be there to check the following logic is correct:

```cpp
  unsigned NewOpc;
  switch (Op.getOpcode()) {
 default:
    return false;
  case ISD::AND:
    NewOpc = Size == 32 ? AArch64::ANDWri : AArch64::ANDXri;
    break;
  case ISD::OR:
    NewOpc = Size == 32 ? AArch64::ORRWri : AArch64::ORRXri;
    break;
  case ISD::XOR:
    NewOpc = Size == 32 ? AArch64::EORWri : AArch64::EORXri;
 break;
  }
```

which could be updated to check for `Size <= 32`: use `W` registers else use the `X` registers, I can create a PR for this change if someone can confirm I am correct, thanks!
</pre>
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