<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/123065>123065</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AMDGPU][GISel] FMin fmax pattern not recognize
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:globalisel
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          qcolombet
      </td>
    </tr>
</table>

<pre>
    The attached reproducer lowers with compares and selects with GISel whereas SDISel uses fmin and fmax resulting in a shorter and more efficient code sequence.
SDISel seems to perform the simplification as part of its IR building process.

# To Reproduce #

Download the attached reproducer or copy/paste the IR below. 
[repro.ll.txt](https://github.com/user-attachments/files/18426310/repro.ll.txt)

Then run:
```bash
llc -O3 -march=amdgcn -mcpu=gfx942  -mtriple amdgcn-amd-hmcsa -global-isel=<0|1> repro.ll -o -
```

# Result #

GISel:
```asm
        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
        v_and_b32_e32 v1, 1, v1
        v_cmp_ne_u32_e32 vcc, 0, v1
        v_mov_b32_e32 v1, 0x57f0
        s_nop 0
        v_cndmask_b32_e32 v0, 0, v0, vcc
        v_cmp_le_f16_e32 vcc, v0, v1
        s_nop 1
        v_cndmask_b32_e32 v0, v1, v0, vcc
        v_cvt_f32_f16_e32 v0, v0
        v_cvt_i32_f32_e32 v2, v0
        v_mov_b64_e32 v[0:1], 0
        global_store_byte v[0:1], v2, off
        s_waitcnt vmcnt(0)
        s_setpc_b64 s[30:31]
```

SDISel:
```asm
        s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
        v_and_b32_e32 v1, 1, v1
        v_cmp_eq_u32_e32 vcc, 1, v1
        s_nop 1
        v_cndmask_b32_e32 v0, 0, v0, vcc
        v_max_f16_e32 v0, v0, v0
        v_min_f16_e32 v0, 0x57f0, v0
        v_cvt_i16_f16_e32 v2, v0
        v_mov_b64_e32 v[0:1], 0
        global_store_byte v[0:1], v2, off
        s_waitcnt vmcnt(0)
        s_setpc_b64 s[30:31]
```

# Note #

Input:
```llvm
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
target triple = "amdgcn-amd-amdhsa"

define void @foo.bb848(<1 x half> %i888, <1 x i1> %0, <1 x i1> %1) {
newFuncRoot:
  %i924 = select <1 x i1> %0, <1 x half> %i888, <1 x half> zeroinitializer
  %.inv24 = fcmp ole <1 x half> %i924, splat (half 0xH57F0)
  %i932 = select <1 x i1> %.inv24, <1 x half> %i924, <1 x half> splat (half 0xH57F0)
  %i940 = fptosi <1 x half> %i932 to <1 x i8>
  store <1 x i8> %i940, ptr addrspace(1) null, align 1
  ret void
}
```

The problem was reduced to make it easier to debug, but the original issue was using a vector of size 4.
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzUVs-T46oR_mvwpUsuAZJsHXzwjJ83e3hJandzdiHUssgi0ALSzO5fnwLZM54fO6mcUq_KhQxf6-sPumm18F6dDeKOlHekPKzEFHrrdj-k1XZoMKwa2_7cfesRRAhC9tiCw9HZdpLoQNsHdB4eVOhB2mEUDj0I04JHjTJckE-fv6KGhx4dCg9fD2k6efTQDcok-24Qj-DQTzooc4a4Cr63LqBL-GAdAnadkgpNAGlbBI8_JjQS1yTfX0g94uAhWBjRddYNEHoEr4ZRq05JEZQ1IDyMwgWwHajg4fMXaCal2-h2dFai95Ew_hiHbxa-XLcLhPEFOdgHo61oE_1752IdSDv-JOw4Ch8w2UVHqO3DGiJJeZfM11qvw2Mg5YGwbR_C6AnfE3Yk7HhWoZ-atbQDYcfJo8sWTwOa4Ak7dkpjfNJtwSpOc8KOLyhZvYj91qMBN5lInO9JlS-_Rvie5HutJWT_4JANwsme8IMY2rM0kA1ynAg_nLvHumAA2RCcGjXCgmdiaLN-kF5Adta2ETpTHjXhB8Lvc7K5p4T_AVc9kFnIbp0_H_CXFPPno0258kqq8EMCa396ECpIE2AepAmEbXPCasDH8Wamz99vwOXF-SRMe2o4OyFnMFPC7iENM70ayGE8GTxNVxspI56_NBrs_Iolfyw3XX6VZ-wI-ROjaQfhvz-_kD8zLqOUt941njpa3XqfX7hf6OnH9Iuqt_xzOHWcPTu4yrjBVcSvZOwlnjZeFQtGyruc8D1NWXt_3fCSBicfrMNT8zPgG8OF1HbdR9G8Yh7DKKNP8KS845GHJ6I3abTc_f9XzuCP1zlD_-egvZ8Tg3h8G6-XUVHmlcUlHd_GllbPln-h2MYS8XcbbmrvZzNO4VWwtZ5jtINwZwzQiiC0-GmnAIQfgDCG2Uj4virSkI30dsKi82XIRn47KW7Nylukup1s4ilUcQ-srJ7GiGwjwi5jNtbxT83eGqqrl5lWiSybWbFA89XNXGwvNnV1IZyfyLL5iTGbSxpXS8qymeaJJz6ymeWJIj4yk2irIvvKWbYvs080M4rwfdxLNKoJY88Heqn8l8O8-QCIoe29WGxJvm-xUwZhtqoFUuSdteum2RZbEs_gnsIj9EJ38cNAWKm2221MmQui6GU9f2-RxktKNnck3xt8OE5GfrH2kgWQ2GpWJIFL4_Eh6-9FXJFf6KwyKiih1S90VydrZeaLm04OI9h0KG84a1ZETj9qET9s24hB_vi3cnO8XIKLZM4-krx4-43u-l3kv7ss8kX-GKxX7xJzFvunq5gt4X-kt9PVf7F8JYw6xuBAtK3zo5BI2DbFy0xaR1BodTapBAI4DCk_YsJs3rnvsdEcnW00DvAgPDiMDVUbJQ3iO4IKgMIrdHGlxWY6Rw_NFFKLZZ06KyM0KO8nTASTj42dgBllsC42fV79QijWq3bH25rXYoU7uuFVXXK2pat-V1RVkbfbtqa8zmve5nIjEWlXs5oKvhErtWM5K3NKS1rmlNF1VWyrCmneCkYxbxpS5DgIpdexLq2tO6-Snh1lPK_KlRYNap8absZS6eL7pcCmFoqx2Ie7XUSyZjp7UuRa-eCf6YIKOnXs-z8Pn_75r1g5y7ulcyoPcPxTmaWhHkUI6AwYG8ChtGejfuFqcnr3QauZFC2PbHT23ygDYce0g9RuLpuYd-w_AQAA___2MIGJ">