<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/122422>122422</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64][SVE] can improve SIMD immediate generation
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          k-arrows
      </td>
    </tr>
</table>

<pre>
    Test case:
```c
#include <arm_neon.h>

typedef short v8hi __attribute__((vector_size(16)));
typedef int v4si __attribute__((vector_size(16)));
typedef long v2di __attribute__((vector_size(16)));

v4si t1 ()
{
  return (v4si) { 0xffc, 0xffc, 0xffc, 0xffc };
}

v8hi t2 ()
{
  return (v8hi) { 510, 510, 510, 510, 510, 510, 510, 510 };
}

v2di t3 ()
{
  return (v2di) { 1, 1 };
}

```

When generating Advanced SIMD code, if SVE is available on target CPU, SVE move immediate can be used.
https://godbolt.org/z/9vhc6Mx1j

The same applies for SVE bitmask immediate.

Reference(GCC patches): 
[AArch64: Improve SIMD immediate generation (1/3)]
[AArch64: Improve SIMD immediate generation (2/3)]
[AArch64: Add support for SIMD xor immediate (3/3)]
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJyklM9u3DYQxp-Gugy8oEb_Dzpod71FDgGKOk2PC4ocSUwkUSApxcnTF5Q3dlCkLuoABLgkh79vZvYThXO6n4lqlh1Zdo7E6gdj6893wlrzxUWtUV_rD-Q8SOGIJQ3jDcv505BhgYme5bgqApachJ2uM5n5MLDkPpzyxn9dSFEHbjDWw1YOGq5X4b3V7erpemVYMiw3kt7Yq9PfiGEZ5wyr20iOP0D07GFL3a8gRjP3sKF6C4PxZlf3MezxVdgrwgmAJb_aOeyHEIYVsOII_LHrJMPTv_0AVpxv7OJ8Uwgt8viqQjk8K2QxD7T_Nf1MNXTEJ6-qonpWjQMp_gnn2RxPy78GmqGnmazweu6hUZuYJSl4ePf-DNIoCiDdwcPHe9AOxCb0KNqRwMzghe3Jw-n3P0NQiJjMRqCniZQWnkCKGVqC1ZE6MN4M3i8ueBQvDC-9Ua0Z_cHYnuHlG8NLtQ0yf_8Yf3rK7cNA4MREIJZl1OSgM3ZXabWfhPv8InR4uvAHdWRplsEbv51OsAgvB3K7PRoIMdmxaawc8jRsvJsWG_LdS31J-ns3zN7UmOElCYTs_DYAvgJolAK3Lkv48vbiAujR2B9gDMvkhRCpOlFVUomI6rhI8rQsUl5FQ61yxYu87PJclF1GMq44iphnlMRtWxVppGvkmPE45jxL8rQ6xJh0Ki5ykWQyqUTGUk6T0ONhHLcp_CmRdm6lOkZMEaNRtDS6_RlCnOkL7KcMMWRl63Dprl17x1I-aufdC8ZrP-7v1_fCszPLjg8f71l23h2i_6uN0WrH-h_m0X5Y24M0E8NLkLpNd4s1n0h6hpc9Qcfwcqtgq_HvAAAA__-GwI_V">