<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/122212>122212</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
failed to legalize operation 'memref.global' that was explicitly marked illegal
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
pyl3000
</td>
</tr>
</table>
<pre>
The conversion from memref::GlobalOp to emitc.global (emitc::GlobalOp) is already implemented in MemRefToEmitC.cpp
[https://github.com/llvm/llvm-project/blob/783dc59b3ba16a785f48d0b58bf8c9f26a744aac/mlir/lib/Conversion/MemRefToEmitC/MemRefToEmitC.cpp](url)
, so why the following error? How to solve it?
the input file as follow：
```
#map = affine_map<(d0, d1) -> (d0 + d1)>
module {
memref.global "private" @global_seed : memref<i64> = dense<0>
func.func @torch.aten.convolution$nobias(%arg0: tensor<1x24x16x128x128xf16>, %arg1: tensor<54x24x1x1x1xf16>) -> tensor<1x54x16x128x128xf16> {
%c24 = arith.constant 24 : index
%c128 = arith.constant 128 : index
%c16 = arith.constant 16 : index
%c54 = arith.constant 54 : index
%c1 = arith.constant 1 : index
%c0 = arith.constant 0 : index
%cst = arith.constant 0.000000e+00 : f32
%0 = bufferization.to_memref %arg1 : memref<54x24x1x1x1xf16, strided<[?, ?, ?, ?, ?], offset: ?>>
%1 = bufferization.to_memref %arg0 : memref<1x24x16x128x128xf16, strided<[?, ?, ?, ?, ?], offset: ?>>
%alloc = memref.alloc() {alignment = 64 : i64} : memref<1x54x16x128x128xf32>
emitc.for %arg2 = %c0 to %c1 step %c1 {
emitc.for %arg3 = %c0 to %c54 step %c1 {
emitc.for %arg4 = %c0 to %c16 step %c1 {
emitc.for %arg5 = %c0 to %c128 step %c1 {
emitc.for %arg6 = %c0 to %c128 step %c1 {
memref.store %cst, %alloc[%arg2, %arg3, %arg4, %arg5, %arg6] : memref<1x54x16x128x128xf32>
}
}
}
}
}
emitc.for %arg2 = %c0 to %c1 step %c1 {
emitc.for %arg3 = %c0 to %c16 step %c1 {
emitc.for %arg4 = %c0 to %c128 step %c1 {
emitc.for %arg5 = %c0 to %c128 step %c1 {
emitc.for %arg6 = %c0 to %c54 step %c1 {
emitc.for %arg7 = %c0 to %c1 step %c1 {
emitc.for %arg8 = %c0 to %c1 step %c1 {
emitc.for %arg9 = %c0 to %c1 step %c1 {
emitc.for %arg10 = %c0 to %c24 step %c1 {
%3 = affine.apply #map(%arg3, %arg7)
%4 = affine.apply #map(%arg4, %arg8)
%5 = affine.apply #map(%arg5, %arg9)
%6 = memref.load %1[%arg2, %arg10, %3, %4, %5] : memref<1x24x16x128x128xf16, strided<[?, ?, ?, ?, ?], offset: ?>>
%7 = memref.load %0[%arg6, %arg10, %arg7, %arg8, %arg9] : memref<54x24x1x1x1xf16, strided<[?, ?, ?, ?, ?], offset: ?>>
%8 = memref.load %alloc[%arg2, %arg6, %arg3, %arg4, %arg5] : memref<1x54x16x128x128xf32>
%9 = arith.extf %6 : f16 to f32
%10 = arith.extf %7 : f16 to f32
%11 = arith.mulf %9, %10 : f32
%12 = arith.addf %8, %11 : f32
memref.store %12, %alloc[%arg2, %arg6, %arg3, %arg4, %arg5] : memref<1x54x16x128x128xf32>
}
}
}
}
}
}
}
}
}
%alloc_0 = memref.alloc() {alignment = 64 : i64} : memref<1x54x16x128x128xf16>
emitc.for %arg2 = %c0 to %c1 step %c1 {
emitc.for %arg3 = %c0 to %c54 step %c1 {
emitc.for %arg4 = %c0 to %c16 step %c1 {
emitc.for %arg5 = %c0 to %c128 step %c1 {
emitc.for %arg6 = %c0 to %c128 step %c1 {
%3 = memref.load %alloc[%c0, %arg3, %arg4, %arg5, %arg6] : memref<1x54x16x128x128xf32>
%4 = arith.truncf %3 : f32 to f16
memref.store %4, %alloc_0[%arg2, %arg3, %arg4, %arg5, %arg6] : memref<1x54x16x128x128xf16>
}
}
}
}
}
%2 = bufferization.to_tensor %alloc_0 : memref<1x54x16x128x128xf16>
return %2 : tensor<1x54x16x128x128xf16>
}
func.func @q_conv_test(%arg0: tensor<?x?x?x?xi8>, %arg1: tensor<?x?x?x?xi8>, %arg2: tensor<?xf32>) -> tensor<?x?x?x?xf32> {
%c1 = arith.constant 1 : index
%c3_i32 = arith.constant 3 : i32
%c7_i32 = arith.constant 7 : i32
%cst = arith.constant 1.000000e-04 : f64
%cst_0 = arith.constant 0.000000e+00 : f32
%c3 = arith.constant 3 : index
%c2 = arith.constant 2 : index
%cst_1 = arith.constant 2.14748365E+9 : f32
%cst_2 = arith.constant -2.14748365E+9 : f32
%c0 = arith.constant 0 : index
%c1_i64 = arith.constant 1 : i64
%0 = bufferization.to_memref %arg1 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%1 = bufferization.to_memref %arg0 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%2 = bufferization.to_memref %arg1 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%3 = bufferization.to_memref %arg1 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%4 = bufferization.to_memref %arg1 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%5 = bufferization.to_memref %arg0 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%6 = bufferization.to_memref %arg0 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%7 = bufferization.to_memref %arg0 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%8 = bufferization.to_memref %arg2 : memref<?xf32, strided<[?], offset: ?>>
%9 = bufferization.to_memref %arg2 : memref<?xf32, strided<[?], offset: ?>>
%dim = memref.dim %9, %c0 : memref<?xf32, strided<[?], offset: ?>>
%alloc = memref.alloc(%dim) {alignment = 64 : i64} : memref<?xi32>
%dim_3 = memref.dim %8, %c0 : memref<?xf32, strided<[?], offset: ?>>
emitc.for %arg3 = %c0 to %dim_3 step %c1 {
%21 = memref.load %8[%arg3] : memref<?xf32, strided<[?], offset: ?>>
%22 = arith.truncf %cst : f64 to f32
%23 = arith.divf %21, %22 : f32
%24 = math.roundeven %23 : f32
%25 = arith.addf %24, %cst_0 : f32
%26 = arith.maximumf %25, %cst_2 : f32
%27 = arith.minimumf %26, %cst_1 : f32
%28 = arith.fptosi %27 : f32 to i32
memref.store %28, %alloc[%arg3] : memref<?xi32>
}
%alloc_4 = memref.alloc(%dim) {alignment = 64 : i64} : memref<?xf32>
emitc.for %arg3 = %c0 to %dim step %c1 {
%21 = memref.load %alloc[%arg3] : memref<?xi32>
%22 = arith.sitofp %21 : i32 to f32
%23 = arith.truncf %cst : f64 to f32
%24 = arith.mulf %22, %23 : f32
memref.store %24, %alloc_4[%arg3] : memref<?xf32>
}
emitc.for %arg3 = %c0 to %dim step %c1 {
%21 = memref.load %alloc_4[%arg3] : memref<?xf32>
%22 = arith.truncf %cst : f64 to f32
%23 = arith.divf %21, %22 : f32
%24 = math.roundeven %23 : f32
%25 = arith.addf %24, %cst_0 : f32
%26 = arith.maximumf %25, %cst_2 : f32
%27 = arith.minimumf %26, %cst_1 : f32
%28 = arith.fptosi %27 : f32 to i32
memref.store %28, %alloc[%arg3] : memref<?xi32>
}
%dim_5 = memref.dim %7, %c0 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%dim_6 = memref.dim %6, %c2 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%dim_7 = memref.dim %5, %c3 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%dim_8 = memref.dim %4, %c0 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%dim_9 = memref.dim %3, %c2 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%dim_10 = memref.dim %2, %c3 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%10 = arith.index_cast %dim_9 : index to i64
%11 = arith.index_cast %dim_6 : index to i64
%12 = arith.subi %10, %c1_i64 : i64
%13 = arith.subi %11, %12 : i64
%14 = arith.index_cast %13 : i64 to index
%15 = arith.index_cast %dim_10 : index to i64
%16 = arith.index_cast %dim_7 : index to i64
%17 = arith.subi %15, %c1_i64 : i64
%18 = arith.subi %16, %17 : i64
%19 = arith.index_cast %18 : i64 to index
%alloc_11 = memref.alloc(%dim_5, %dim_8, %14, %19) {alignment = 64 : i64} : memref<?x?x?x?xi32>
emitc.for %arg3 = %c0 to %dim_5 step %c1 {
emitc.for %arg4 = %c0 to %dim step %c1 {
emitc.for %arg5 = %c0 to %14 step %c1 {
emitc.for %arg6 = %c0 to %19 step %c1 {
%21 = memref.load %alloc[%arg4] : memref<?xi32>
memref.store %21, %alloc_11[%arg3, %arg4, %arg5, %arg6] : memref<?x?x?x?xi32>
}
}
}
}
%dim_12 = memref.dim %1, %c0 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%dim_13 = memref.dim %1, %c1 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%dim_14 = memref.dim %0, %c0 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%dim_15 = memref.dim %0, %c2 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%dim_16 = memref.dim %0, %c3 : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
emitc.for %arg3 = %c0 to %dim_12 step %c1 {
emitc.for %arg4 = %c0 to %dim_14 step %c1 {
emitc.for %arg5 = %c0 to %14 step %c1 {
emitc.for %arg6 = %c0 to %19 step %c1 {
emitc.for %arg7 = %c0 to %dim_13 step %c1 {
emitc.for %arg8 = %c0 to %dim_15 step %c1 {
emitc.for %arg9 = %c0 to %dim_16 step %c1 {
%21 = affine.apply #map(%arg5, %arg8)
%22 = affine.apply #map(%arg6, %arg9)
%23 = memref.load %1[%arg3, %arg7, %21, %22] : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%24 = memref.load %0[%arg4, %arg7, %arg8, %arg9] : memref<?x?x?x?xi8, strided<[?, ?, ?, ?], offset: ?>>
%25 = memref.load %alloc_11[%arg3, %arg4, %arg5, %arg6] : memref<?x?x?x?xi32>
%26 = arith.extsi %23 : i8 to i32
%27 = arith.subi %26, %c7_i32 : i32
%28 = arith.extsi %24 : i8 to i32
%29 = arith.subi %28, %c3_i32 : i32
%30 = arith.muli %27, %29 : i32
%31 = arith.addi %25, %30 : i32
memref.store %31, %alloc_11[%arg3, %arg4, %arg5, %arg6] : memref<?x?x?x?xi32>
}
}
}
}
}
}
}
%alloc_17 = memref.alloc(%dim_5, %dim_8, %14, %19) {alignment = 64 : i64} : memref<?x?x?x?xf32>
emitc.for %arg3 = %c0 to %dim_5 step %c1 {
emitc.for %arg4 = %c0 to %dim_8 step %c1 {
emitc.for %arg5 = %c0 to %14 step %c1 {
emitc.for %arg6 = %c0 to %19 step %c1 {
%21 = memref.load %alloc_11[%arg3, %arg4, %arg5, %arg6] : memref<?x?x?x?xi32>
%22 = arith.sitofp %21 : i32 to f32
%23 = arith.truncf %cst : f64 to f32
%24 = arith.mulf %22, %23 : f32
memref.store %24, %alloc_17[%arg3, %arg4, %arg5, %arg6] : memref<?x?x?x?xf32>
}
}
}
}
%20 = bufferization.to_tensor %alloc_17 : memref<?x?x?x?xf32>
return %20 : tensor<?x?x?x?xf32>
}
func.func @conv_broadcast(%arg0: tensor<1x80x3000xf32>, %arg1: tensor<1024x80x3xf32>, %arg2: tensor<1024xf32>) -> tensor<1x1024x3000xf32> {
%c3 = arith.constant 3 : index
%c3000 = arith.constant 3000 : index
%c1024 = arith.constant 1024 : index
%c3002 = arith.constant 3002 : index
%c80 = arith.constant 80 : index
%c1 = arith.constant 1 : index
%c0 = arith.constant 0 : index
%cst = arith.constant 0.000000e+00 : f32
%0 = bufferization.to_memref %arg0 : memref<1x80x3000xf32, strided<[?, ?, ?], offset: ?>>
%1 = bufferization.to_memref %arg1 : memref<1024x80x3xf32, strided<[?, ?, ?], offset: ?>>
%2 = bufferization.to_memref %arg2 : memref<1024xf32, strided<[?], offset: ?>>
%alloc = memref.alloc() {alignment = 64 : i64} : memref<1x80x3002xf32>
emitc.for %arg3 = %c0 to %c1 step %c1 {
emitc.for %arg4 = %c0 to %c80 step %c1 {
emitc.for %arg5 = %c0 to %c3002 step %c1 {
memref.store %cst, %alloc[%arg3, %arg4, %arg5] : memref<1x80x3002xf32>
}
}
}
%subview = memref.subview %alloc[0, 0, 1] [1, 80, 3000] [1, 1, 1] : memref<1x80x3002xf32> to memref<1x80x3000xf32, strided<[240160, 3002, 1], offset: 1>>
memref.copy %0, %subview : memref<1x80x3000xf32, strided<[?, ?, ?], offset: ?>> to memref<1x80x3000xf32, strided<[240160, 3002, 1], offset: 1>>
%alloc_0 = memref.alloc() {alignment = 64 : i64} : memref<1x1024x3000xf32>
emitc.for %arg3 = %c0 to %c1 step %c1 {
emitc.for %arg4 = %c0 to %c1024 step %c1 {
emitc.for %arg5 = %c0 to %c3000 step %c1 {
%4 = memref.load %2[%arg4] : memref<1024xf32, strided<[?], offset: ?>>
memref.store %4, %alloc_0[%arg3, %arg4, %arg5] : memref<1x1024x3000xf32>
}
}
}
emitc.for %arg3 = %c0 to %c1 step %c1 {
emitc.for %arg4 = %c0 to %c1024 step %c1 {
emitc.for %arg5 = %c0 to %c3000 step %c1 {
emitc.for %arg6 = %c0 to %c80 step %c1 {
emitc.for %arg7 = %c0 to %c3 step %c1 {
%4 = affine.apply #map(%arg5, %arg7)
%5 = memref.load %alloc[%arg3, %arg6, %4] : memref<1x80x3002xf32>
%6 = memref.load %1[%arg4, %arg6, %arg7] : memref<1024x80x3xf32, strided<[?, ?, ?], offset: ?>>
%7 = memref.load %alloc_0[%arg3, %arg4, %arg5] : memref<1x1024x3000xf32>
%8 = arith.mulf %5, %6 : f32
%9 = arith.addf %7, %8 : f32
memref.store %9, %alloc_0[%arg3, %arg4, %arg5] : memref<1x1024x3000xf32>
}
}
}
}
}
%3 = bufferization.to_tensor %alloc_0 : memref<1x1024x3000xf32>
return %3 : tensor<1x1024x3000xf32>
}
}
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJzsXElv6zqy_jXMhojBQePCCyfn-L23eGigcfeGLFExuzW4JTnD_fUNUrNUGpzESbpxc04Sm2EVP5I1sVS0l-fyKRFii8wHZP668y7FKc2257eIE0Lujmnwtv3jJLCfJs8iy2Wa4DBLYxyLOBMh4jvEd_8TpUcv-tsZFykWsSz8zZNuwYg5-n2_G2Iuljn2okx4wRuW8TkSsUgKEWCZ4P8X8d9F-Ef6O5bF48Y_nxHZIfPhVBTnXPFhe8T2T7I4XY4bP40R20fRc_3r_pyl_xB-gdj-GKVHxPa2wwPfdI_86FHLsx0zNJyAHE3nGDq-GzLLsw3D83zE9nEkM8VHKrrHZr6I7XuYhu81RvMXYs4lixBzFV72iPMUv5zecHESOEyjKH2RyRMWWZZmiO_x_6YvarXyNHoWWBaI7xWZoqTIfPi_2HsSJc-ZeV9ykd17ReH5J7V8OWJ7L8-FfhEy4QaMWve-y_x7w3DE_dFgxj2zHYtyylzhuBVWslMYZXK-FDiUkcBeXiFGv_fo4RG5uwqbRar_CiePvTNG_Bf2wlAm4hB7Z8QfEXMCoqYfULXN94j_xroNI_ZQNiL-G5FdnAaXSGBkPyCyw5U4tXLDzpl89gqBGMPIIGX7IRciwIjvGul7lJahh-C_cCCSXCD-SMoBMA4vib9RPxSHIs3808YrRLJRopxGl0LvrZGkR-nliDmImV72RBT7QiS52qdH-sqMV2q9Uubo75Baijt7xGVv2uttGrq7_lf3rNagw9EEODbrgBVjnxnlymayOCm4eeElBdatOyyTQLx2OlPmQL3LZqC7Bfa2wM4mCMScAAIyBrsSqCsBu-YF2HdD9JdA7IGUhCFnLVk5wPEShiKTf3pqrzdFeijlpt68vigNd0_pcJHJQARKrs0HpaNq46d-KXV9xGkY5qJQjFUb_10Lo0ZFV6AifVSQBN4AmRdFqa_RVZqoG7RWuEo4vUg-JcrK6D5WJQCWgexfQ7wD-easHah0DmGaVXNlmlspEEVaCVFeiHMtT41WjGn5mNY0pojH5AYwtDVNPmZgAgyYM8dhzMN6B4_GVuZFmolKRWqLpDfNfKhWt7VTvH1ptC_N9qWFzGs2sv5C9q9eS_999137un11Y3GY28814jC_E18kD3MyDTOxr1jFaS7Ou7iM-bjv5DPmRMmYFVtcnUYWmck74crGO5-jN1yGMY3z76iJXUZHk8yMRWYdRXMWmJmLzDqq6i4ws7pmPEq9QHseyCpQUr2u511DNgFrcHs3BM7GhmZDmtlYwGzK3eusfbtyw2nd2ueDU3KgKU2abmvZir_LdPcguZ0YS7wWYS1HOxxSSylbG1yB9JQADOxrGHSDx_gSaQZuNUk6DPBgFqzDwgsCzaLefUoXWQzdKmVLXvXWWzP0rvPtUOu47WMeu16NA7lJrFiemf6KFSEe74sVG7c3bW58cvs4sesytX4W2SXxwxqeVkxtJai1GO4aXbU8kFuFu11Z_DTlYfABsMwO9LVrLbZMFJcsqZnvljINmqrG1MuQ_Ovgp8nzoRDqOAFmQxDfv3a_pTOTDFnozEadK8EZZUyGjMp-g4zJFbkHfpCcQd1LSZTdNIJvT3W2gc5wqoLWqYp7UprC0DJ6RAc4G7KQ4fD5zBwGUwZnwCbSLQdwLdmGGrbhcMv8jdiDC-DJiwM4zv0y6RXpIHqQFpiUoo2b-UgSCJDa1THhbRJAN0Y0YZG-cY34j0Nk_DhE5o-TI-vHIbJ_HCJnBSI2RqRsJQRjxYjul48YyLgbb-q37UnOBxb8A4PNZK0VkGvPI3rLu-FryebAgRk5N5jR8rGlRDMR8ytrTqFg32liZD6Kez-CtxySgWF9GQzpYGd4_FdE3eAlkM9hCb5aU8ZGh3XVWprh2CtOmyy9JIF4FknDbNzdBNIBrD4O1GHXmKz7eCz2XmV8iUtSs0MKA7S7pDJpSa0O6TgRoXp0H-GF5yLNZcOxORzJDs3wUMQcMFkB73dfxseHe-NzVWr2ERAo41dL-NWzHotuLos0PDdD6Nh-SXJXi7sBZLdYfWAF5He0vf1Dr7FCoYENvuHaXwfpL8Px32Y4lGMyATdpz7jJG0ZaCo4FwGnWEwh6bgzHBuA0ksG_HI4DwDG-b7NcAA7_vs2iBMDDvme3es9WdDrk4HvKSLYrV6VJtK53EyC9pypjUmuOtOcbL0dZQqmXoE7DDDIulENUtXmmDKAwJiFSXnfX6PqJIGrOTo2SublZs7T2HKkNTdBcWhYHoqqNEbUBCnd6WZyZZSmdMaXTEdyhBqutQA2hVn3qvifC60n_1dHewVz7HGf8IGYmYFnzGIbO1g8sP4Kh7vwDmJUBq7EmYJ3w37QXGVLaceFXPwSZ3ctqRtc-8tDayABzSr_P21DoRN_g-dpUnsZjAHjIN64PFMqRb3THUCxHvsEdr7NnlH3IoB3mrNL327TlerNKxa6sWxtXnFWieHXt2rjmrBKiFbVircVeWY41WdvVOeLOcOrUkEwWdrXn3smqrn7l2iPun4qXDf0n6sgYuzFfw2WMsS_VbX0tfnM67XFzf9vFYfWLrKqjfhUlO8OT_pAailzbBEP9oHs3y8MBERgrEbgQgiaRztcg4KSfSauyHbWku4v0tJ_cKenrTeJkln4Ye_Evjr2qWXxlnRe1v-8kcX3e-IMnicNMOdX3-92FBOwXSN97UuYt5dWJ85b02vQ5rK6DJDq1P3PBgLK366vDJgpWhuVhVcJgHZZOfRjBsxVaHTKwQEyXhx2z1At8b7JGjL465JUTQpp6Lrg8jBJm6K6jfmzcb6o0jL7qP3eGG5SFXVEjpZiAvQmZqEQi8DW9qh0cAa47K9vHBA4IyJmAs74C7kfcvhvVOHblZjmY-6Riq8FZvy-Vn4JiTYEVA1Dcpizi2gLtclPYtb54fWk2UFvtkI-44VLNZjzp2utz60v6wUVaafPzy_FZipfubjVNLSKd69A_qB7ffNChp6OblNZ0W2nbbw6nWq-V6scMQq16LFaz78sh7UlhNRU_Pb_hTq6mne0tVP-mM_rsqw9Dz_U1uqWd0we1a0Y9O-WSgyCVzSS7P2TvYKWeuiSwXqkn9meNWv-n7-GKqydzNhpiAVxKXUwQrrplafaSR-P8WVMsu1AxxIaXugAxnTb0zVgLly-N8TgaOKgRnxiH9DCCVypvoijNkA5wgKt3zpq8mTe4mFjX4tTZHmeScGgN3Ftag6FFGL9fEQZMFL0vXgyawNUe-vjwUhBIUWKpfnY_5oXs7oItD1zuendiS21ucZebjnl32lLmMC88BoZwPGoyylzbINw0bcOmwnL5ndwywkxCiUs458TcMINTy7aZG9iGG9IjMoiIPRltoug53qTZ053M84vYUsYYZXeRdxRRrj-YiLFEvGD9V6TT2XfZVn_ez_HylCODRDIv8pZNIYtIbENPRiJQ5iYST14k_xQ4PYtMLy5GzK6kpPxsGcRsXJy8Ar94ORav50j6sojecOxl_xQBlpHmcXfJou3VH0WkceeI7auJPW_ZvwMAAP__prUoIQ">