<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/122092>122092</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [Clang] Intel Assembly Bug (Mishandle Vector Register Names)
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            clang
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          witbring
      </td>
    </tr>
</table>

<pre>
    I am reporting an assembly bug found during research.
The tests were conducted using the latest version (Clang 19.1.0)
The issue occurs in the same way with previous versions as well.

When vertor register names are used in memory operands, incorrect binary code is generated.
Clang converts them 64-bit registers in x86-64, while converting them 32-bit registers in x86.

1. Example Code

```
.intel_syntax noprefix
.data
xmm0:
ymm0:
zmm0:
    .long 0

.text
test:
    mov edx, DWORD PTR [xmm0]
    mov     edx, DWORD PTR [ymm0]
    mov     edx, DWORD PTR [zmm0]
```

2. Compilation Command

```
clang -c test.s
```

3. Compiled Binary Output

```
0000000000000000 <test>:
 0:   8b 14 05 00 00 00 00    mov    edx,DWORD PTR [rax*1+0x0]
   7:   8b 14 05 00 00 00 00    mov    edx,DWORD PTR [rax*1+0x0]
   e:   8b 14 05 00 00 00 00    mov    edx,DWORD PTR [rax*1+0x0]
```

This related bug can also be observed when we use any vector register names.

This bug can also be reproduced on Godbolt:
https://godbolt.org/z/br7n44ezr
</pre>
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