<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/122093>122093</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [Clang] Intel Assembly Bug (Mishandle RIP-relative Addressing)
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          witbring
      </td>
    </tr>
</table>

<pre>
    I am reporting another assembly bug found during research. 
The tests were conducted using the latest version (Clang 19.1.0)
The issue occurs in the same way with previous versions as well.

When register names are used in RIP-relative addressing, Clang converts them register indirect addressing.

1. Example Code

```
.intel_syntax noprefix
.data
rax:
xmm0:
ymm0:
zmm0:
 .long 0

.text
test:
    mov     edx, DWORD PTR [rip+rax]
    mov edx, DWORD PTR [rip+xmm0]
    mov     edx, DWORD PTR [rip+ymm0]
    mov edx, DWORD PTR [rip+zmm0]
```

2. Compilation Command

```
clang -c test.s
```

3. Compiled Binary Output

```
0000000000000000 <test>:
 0:   8b 14 05 00 00 00 00    mov    edx,DWORD PTR [rax*1+0x0]
   7:   8b 14 05 00 00 00 00    mov    edx,DWORD PTR [rax*1+0x0]
   e:   8b 14 05 00 00 00 00    mov    edx,DWORD PTR [rax*1+0x0]
  15:   8b 14 05 00 00 00 00    mov edx,DWORD PTR [rax*1+0x0]
```

This related bug can also be observed when we use any 32/64/128/256/512-bit register names.

This bug can also be reproduced on Godbolt:
https://godbolt.org/z/sM4d8onor
</pre>
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