<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/121546>121546</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Add a high latency "feature" (hazard) for specific shift instruction operands on Alder Lake and generic x86-64 tunings
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:X86
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          chandlerc
      </td>
    </tr>
</table>

<pre>
    See the detailed discussion:
https://tavianator.com/2025/shlx.html

And some added details:
https://lobste.rs/s/1hbwkk/alder_lake_shlx_anomaly

Basically, when the shift instruction is set using the wrong kind of instruction, it causes a 3x throughput hit.

There should always be other ways to encode this and so it seems worth avoiding in the x86 backend, at least when tuning for Alder Lake or a generic x86 CPU.
</pre>
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