<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/120676>120676</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
The memref dialect cannot be converted to the emitc dialect
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
pyl3000
</td>
</tr>
</table>
<pre>
When I use` mlir-opt .\matmul-emitc2.mlir --convert-memref-to-emitc -o matmul-emitc3.mlir` to drop the memref dialect to the emitc dialect with the error:
Input mlir as follow：
```
module {
func.func @main() {
%0 = "emitc.constant"() <{value = 0.000000e+00 : f64}> : () -> f64
%1 = "emitc.constant"() <{value = 6.000000e+00 : f64}> : () -> f64
%2 = "emitc.constant"() <{value = 5.000000e+00 : f64}> : () -> f64
%3 = "emitc.constant"() <{value = 4.000000e+00 : f64}> : () -> f64
%4 = "emitc.constant"() <{value = 3.000000e+00 : f64}> : () -> f64
%5 = "emitc.constant"() <{value = 2.000000e+00 : f64}> : () -> f64
%6 = "emitc.constant"() <{value = 1.000000e+00 : f64}> : () -> f64
%alloc = memref.alloc() : memref<2x2xf64>
%alloc_0 = memref.alloc() : memref<2x3xf64>
%7 = "emitc.constant"() <{value = 0 : index}> : () -> !emitc.size_t
%8 = builtin.unrealized_conversion_cast %7 : !emitc.size_t to index
%9 = "emitc.constant"() <{value = 0 : index}> : () -> !emitc.size_t
%10 = builtin.unrealized_conversion_cast %9 : !emitc.size_t to index
memref.store %6, %alloc_0[%8, %10] : memref<2x3xf64>
%11 = "emitc.constant"() <{value = 0 : index}> : () -> !emitc.size_t
%12 = builtin.unrealized_conversion_cast %11 : !emitc.size_t to index
%13 = "emitc.constant"() <{value = 1 : index}> : () -> !emitc.size_t
%14 = builtin.unrealized_conversion_cast %13 : !emitc.size_t to index
memref.store %5, %alloc_0[%12, %14] : memref<2x3xf64>
%15 = "emitc.constant"() <{value = 0 : index}> : () -> !emitc.size_t
%16 = builtin.unrealized_conversion_cast %15 : !emitc.size_t to index
%17 = "emitc.constant"() <{value = 2 : index}> : () -> !emitc.size_t
%18 = builtin.unrealized_conversion_cast %17 : !emitc.size_t to index
memref.store %4, %alloc_0[%16, %18] : memref<2x3xf64>
%19 = "emitc.constant"() <{value = 1 : index}> : () -> !emitc.size_t
%20 = builtin.unrealized_conversion_cast %19 : !emitc.size_t to index
%21 = "emitc.constant"() <{value = 0 : index}> : () -> !emitc.size_t
%22 = builtin.unrealized_conversion_cast %21 : !emitc.size_t to index
memref.store %3, %alloc_0[%20, %22] : memref<2x3xf64>
%23 = "emitc.constant"() <{value = 1 : index}> : () -> !emitc.size_t
%24 = builtin.unrealized_conversion_cast %23 : !emitc.size_t to index
%25 = "emitc.constant"() <{value = 1 : index}> : () -> !emitc.size_t
%26 = builtin.unrealized_conversion_cast %25 : !emitc.size_t to index
memref.store %2, %alloc_0[%24, %26] : memref<2x3xf64>
%27 = "emitc.constant"() <{value = 1 : index}> : () -> !emitc.size_t
%28 = builtin.unrealized_conversion_cast %27 : !emitc.size_t to index
%29 = "emitc.constant"() <{value = 2 : index}> : () -> !emitc.size_t
%30 = builtin.unrealized_conversion_cast %29 : !emitc.size_t to index
memref.store %1, %alloc_0[%28, %30] : memref<2x3xf64>
%31 = "emitc.constant"() <{value = 0 : index}> : () -> !emitc.size_t
%32 = builtin.unrealized_conversion_cast %31 : !emitc.size_t to index
%33 = "emitc.constant"() <{value = 2 : index}> : () -> !emitc.size_t
%34 = builtin.unrealized_conversion_cast %33 : !emitc.size_t to index
%35 = "emitc.constant"() <{value = 1 : index}> : () -> !emitc.size_t
%36 = builtin.unrealized_conversion_cast %35 : !emitc.size_t to index
emitc.for %arg0 = %32 to %34 step %36 {
%37 = "emitc.constant"() <{value = 0 : index}> : () -> !emitc.size_t
%38 = builtin.unrealized_conversion_cast %37 : !emitc.size_t to index
%39 = "emitc.constant"() <{value = 2 : index}> : () -> !emitc.size_t
%40 = builtin.unrealized_conversion_cast %39 : !emitc.size_t to index
%41 = "emitc.constant"() <{value = 1 : index}> : () -> !emitc.size_t
%42 = builtin.unrealized_conversion_cast %41 : !emitc.size_t to index
emitc.for %arg1 = %38 to %40 step %42 {
memref.store %0, %alloc[%arg1, %arg0] : memref<2x2xf64>
%43 = "emitc.constant"() <{value = 0 : index}> : () -> !emitc.size_t
%44 = builtin.unrealized_conversion_cast %43 : !emitc.size_t to index
%45 = "emitc.constant"() <{value = 3 : index}> : () -> !emitc.size_t
%46 = builtin.unrealized_conversion_cast %45 : !emitc.size_t to index
%47 = "emitc.constant"() <{value = 1 : index}> : () -> !emitc.size_t
%48 = builtin.unrealized_conversion_cast %47 : !emitc.size_t to index
emitc.for %arg2 = %44 to %46 step %48 {
%49 = memref.load %alloc_0[%arg0, %arg2] : memref<2x3xf64>
%50 = memref.load %alloc_0[%arg1, %arg2] : memref<2x3xf64>
%51 = memref.load %alloc[%arg1, %arg0] : memref<2x2xf64>
%52 = emitc.mul %50, %49 : (f64, f64) -> f64
%53 = emitc.add %51, %52 : (f64, f64) -> f64
memref.store %53, %alloc[%arg1, %arg0] : memref<2x2xf64>
}
}
}
memref.dealloc %alloc_0 : memref<2x3xf64>
memref.dealloc %alloc : memref<2x2xf64>
return
}
}
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJy8mcuO4roWhp_GTKwgeznOZZABl0Kq-ZHOsGQSA9lKYpQ4VdX99FuJk4CA6rbJFi1Egy__b3utfGVs0TT5sZIyQXyN-HYhWn1SdXL-VTBCyGKvsl_J_0-ywu-4bSQKCC6LvPbUWeMl4ptS6LItPFnmOoVlV4U9L1XVp6y1V8qylgdPK1OPPYWv27O-fSepFc5qdcb6JLHphLNcFDLVXVVXagTGwq9cn0xxXasasRUi4wso4uv3Uhwl4lsE0Unrc9O1gB2C3THXp3a_TFWJYNc2svaE1iI9lbLSDYKdaBrZf4giPxWQHTyW0sDzU-CeoIx4YQZhyOghCLIAQWxM36tzq_t1waLBB1UU6gu97dB6g-JxXAEZXmRVqqwtJEbhGpEVxoe2SpfdG0Y-KUVeIYgQxFM9xgg4wYhtMQLoF2KZqqrRotIIYGzNNihcf4qilX1TsiT9P4lgTbreK3wIfBRuEXvrvw39vO57VzNZUVer4GkrcLXiT1sxVyv_aSvf1Yo9bcVdreBpq8DVij5pNTmKolBpL2WYsOwLJrfVUIzYBr7hu1Ngbze9P4hlf3bTf5IJnR-8XjqvMvn9w1wRUCPW5L_lh754Rb3Avs0LnVfLtqqlKPLfMvswQG1yVX2kotHjuFa3Uh0tjfOkGb9w_JQ4TCC2mcAQuEarWvZJiGBzFdzubxbwaCikBPHt3wILnDoDbs6SgMOS9COzCSp1phmdMQXfZQrsmbDyR2GlMMbVt4urMwznxDVwWRRuG1dn2sCMKbjghlrx5jau_sO4jg8xjezi6oywGckOLgijVgzrVF-JHHBBDlgh5zau7FFcgQylAFZxhVdCDFwgBlYQ6xo6I2fOFFyQA1bIuY0rPIzr-BRDYBdXZ4jNWRQXiIHtpgmckTODw8wFOfDUtok-jOu4b2J2-yb2SogxF4gx230Tc0bOnLi6IIfZIoe9EjnMBTnMCjmm7qDqPh_r43iw0UVcq2HdGi3Po_90CmJG9LLfY8bOBS_MCi9G92WAMScSLohhVogxus5IeDYZjZ0LFHwrKNwnJJ0SMhoS0idTQnYjuErIe9KSa9IaznaaY2l9fMTam8OLcbbOsHo-1Y2hC7B8K2CNys7QYjOn4gIu3wpco_LLdjejoQuCfEsE3af9eBTbZcGQ9sEl7aObtDcji68P1wolsrs9Rp_wU-5b_C6YxDmxEadPitMfxWc8s0baLKRZ3rItzFwGLX9Ea9R1hk1_7Hl_BHoRY1diIsvM2AcxDg5idycu7L8CVbi9IHr6fPk0GGdyOM29Ppj9U6x-6PeXEdVSt3XVfzFDGN6vbl8QWS2yhGUxi8VCJjRkfhBwHvLFKaFxxiMZZBEjJJAh4_s9C_ZSpIGk8T6LFnkCBHwKQAhjwPmSRLGUMYgwlgL8NEI-kaXIi2VRfJZLVR8XedO0MqFAgjBYFGIvi6a_awOo5Bfua1H_i3lRJ10nb98eG-STIm90c5HRuS5k8r_7C7JUVJXSeC_xcO0ms4eXZou2LpI_3IZ1TsN_3rlW_8hUI9j142sQ7IYJfCbwbwAAAP__8qja9A">