<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/120355>120355</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Insufficient Optimization of Variadic Functions for Some Targets
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          jonathan-gruber-jg
      </td>
    </tr>
</table>

<pre>
    Clang insufficiently optimizes variadic functions for some target architectures. I only tested the target architectures aarch64 and riscv64, so I'm unsure about other target architectures.

Below is a minimal test case:
```
#include <stdarg.h>

void yes_ap(int dummy, ...) {
        va_list ap;

        va_start(ap, dummy);

        va_end(ap);
}

void no_ap(int dummy, ...) {
        /* Nothing. */
}
```

Host system: Arch Linux, x86_64.

Clang version: official Arch Linux package of clang, version 18.1.8-4.

Command line to reproduce results: clang -c test.c --target=\<arch\> -O\<opt-level\>

aarch64 assembly with -O2, -O3, -Os, or -Oz is along the lines of this:
```
yes_ap:
    sub sp, sp, #0xc0
    stp x1, x2, [sp, #136]
 stp x3, x4, [sp, #152]
    stp x5, x6, [sp, #168]
    str x7, [sp, #184]
 stp q0, q1, [sp]
    stp q2, q3, [sp, #32]
    stp q4, q5, [sp, #64]
 stp q6, q7, [sp, #96]
    add sp, sp, #0xc0
    ret

no_ap:
    sub sp, sp, #0xc0
    stp x1, x2, [sp, #136]
    stp x3, x4, [sp, #152]
    stp x5, x6, [sp, #168]
    str x7, [sp, #184]
    stp q0, q1, [sp]
    stp q2, q3, [sp, #32]
    stp q4, q5, [sp, #64]
    stp q6, q7, [sp, #96]
    add sp, sp, #0xc0
    ret
```

riscv64 assembly with -O2, -O3, -Os, or -Oz is along the lines of this:
```
yes_ap:
    addi sp,sp,-64
    sd a7,56(sp)
    sd   a6,48(sp)
    sd   a5,40(sp)
    sd   a4,32(sp)
    sd a3,24(sp)
    sd   a2,16(sp)
    sd   a1,8(sp)
    addi sp,sp,64
 ret

no_ap:
    addi sp,sp,-64
    sd   a7,56(sp)
    sd   a6,48(sp)
 sd   a5,40(sp)
    sd   a4,32(sp)
    sd   a3,24(sp)
    sd   a2,16(sp)
 sd   a1,8(sp)
    addi sp,sp,64
    ret
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJy8VlFv6ygT_TXkZWTLBtuxH_yQpjf6Kn3aPuxqXysCxKaLIQGcm9xfvwInbZpkr7arq0qV3QyHmXNmBjzUOdlpIVpUPqDycUZH3xvbvhpNfU910tlxLWzy2s3Whh_bpaK6A6nduNlIJoX26ghm6-UgfwgHe2ol5ZLBZtTMS6MdbIwFZwYBntpOeKCW9dIL5kcrXApPYLQ6ghfOCw6-v48DGn5WBVDNwUrH9lWB8BKcgSeE5wOM2o1WAF2b0YPxvbD346FsgbLFg1DmO0gHFAap5UBVJACMOoFIQKAqO_1lC4SJ1EyNXAAiS-c5tV3aI_JtcrY3ksNRuBe6RbiW2gMfh-EY6KVpinADaP4Qoc2evijpPNAtIpPpZHWeWo9wHVwsz_ubK5DQ_AQ5r8wfLyho8y8YILxCeAG_Gd9L3aWA8CKY3nxdys4W_zPOgzs6LwZEFrCwrIf_Sz0egutDXb1UxSmjU1_shXXS6IA1sT-outgEW8r-op0AswEW8MHLaQvkdZqndfLmzwxDqLWSWoA3YMXWGj4yAVa4UXkXYkQnkLBYvJRBkkw1R-QRlUtElqH28b9vkDxPJrP1iRJ7oSb7FO2tu5wTw1od4bv0PSTPODBMnsn0cuFlLCTPP2LvKKO72LGBpAuqfC_dbf-ceiPaAQDcuAYXCz09ESbZgWXnVb-FQx4THMOj8uENlpMKlaFOEyryOhQ3qBKfUGd3ZQRWN8CqvgRaOMxvIHVxEXGXBfMuf0d9iLOLhHfk2gm54rOLlHflNa76ECvS3d0waqp3Z5Tzn2TSCj-VdzoZvzT_Z-CXluCcvi-qwhn3qwrx8W453eJfdOYo53LiFh9JVZwVcqBBWlkhXLt4t74tANCgvajvLoXEFdndpZBZgm-XaFCFi7t7gu78PolQ6WsOV4ImPf_U8T9TD5_U_5_Fwyflf1L7bZ_NeEt4Qxo6E20-J0XRVKQqZ30rMK-rjOSs4mVJigKXBWV0XtWE1IRn-Uy2OMNFjvM6KwguypQ383XDNk0t1ryp6jkqMjFQqVKl9kNqbDeTzo2izXFGynKm6FooF0cqjLUIo4YbBcLhBM5sGzYl67FzqMjCPODe3XjplWifLuYreJ6mKxrGqdDwf55nrNWHGev3MGP9Eb9_bjZa1fbeb-PJCJ_8VSd9P65TZgaEVyHc6ZVsrXkVzCO8iiQdwquTin2L_w4AAP__4d_OPA">