<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/119921>119921</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64] Failure to combine bitwise not of shift into `mvn`
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Kmeakin
      </td>
    </tr>
</table>

<pre>
    https://godbolt.org/z/7sKhdbr4E

The `mvn` (move-not) instruction produces the bitwise not of a shifted/rotated register. GCC recognizes this pattern and produces `mvn`, but clang does not

clang:
```asm
mvn_lsl_1_u8(unsigned char):
        mov     w8, #-1
        eor     w0, w8, w0, lsl #1
 ret

mvn_lsl_1_u16(unsigned short):
        mov     w8, #-1
        eor w0, w8, w0, lsl #1
        ret

mvn_lsl_1_u32(unsigned int):
 mov     w8, #-1
        eor     w0, w8, w0, lsl #1
 ret

mvn_lsl_1_u64(unsigned long):
        mov     x8, #-1
        eor x0, x8, x0, lsl #1
        ret
```

GCC:
```asm
mvn_lsl_1_u8(unsigned char):
        mvn     w0, w0, lsl 1
        ret

mvn_lsl_1_u16(unsigned short):
        mvn     w0, w0, lsl 1
        ret

mvn_lsl_1_u32(unsigned int):
        mvn     w0, w0, lsl 1
        ret

mvn_lsl_1_u64(unsigned long):
        mvn     x0, x0, lsl 1
        ret
```
</pre>
<img width="1" height="1" alt="" src="http://email.email.llvm.org/o/eJy0lM9upDgQxp_GXKxu4QK6mwMHtrPkkOveI2NXwBtjt2xDMnn6kYEkaGbyR5kZC8mIKtevPhf6uPeqM4gVKf4hxVXCx9BbV90MyO-VSVorv1V9CBdPsppAQ6DprGytDnvrOgLNE4Hm6G962br8X5LWJK3_65GSQzpMhhxSSuA02Al3xgYCJVXGBzeKoKyhF2flKNDT0CNtVXhQHqmxgdo7yqnv1V1ASaBxNvCAkjrslA_o9vT6fKYOhe2MeprPK08vPAR0hnIjXyu_9EHgTNsxUKG56ai06CNpaXj-FvWldcycH-4HktbDZG6117fsdjwROI1mvixJRc8dgXI5Q9c12GneH04RRiDbsU0UrVuicytLzvKuvY7Zc7LDtacNmR22aN9bF77Afp-7rl_hM9jildnA_5biQ75Famu6NwU_vol-nFFL_PEDwc9TXzq5Pp__wN8wma36lwY-uu5PTfuLtd8Z5W9W_szE1tLrXN4r_XztiawyWWYlT7BixyxnwPI8T_qKF6kU7CjzNmfsyNPsTgjgh1OLRX4EJhJVQQoxP4t7mu-P2QGBSVliIWVaSJKnOHCl91pPQ_SyRHk_YsVYWQJLNG9R-9kUAVou7tFIktV17UQftQKBMwEYlPcod_YS1KCeeHS1GCuuElfFwrt27DzJU6188K-ooIKeHfe5XnFFG6706JAGS4UdWmV-ssTZEOPU7KutJaPTP_qzCv3Y7oUdCDQRuW67i7P_owgEmlmqJ9CsaqcKvgcAAP__DwC5_Q">