<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/118132>118132</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64] Combine `and` and `lsl` into `ubfiz`
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Kmeakin
      </td>
    </tr>
</table>

<pre>
    https://godbolt.org/z/jxbMMs3dP

```c
uint64_t u8(uint8_t x) { return x << 1; }
uint64_t u16(uint16_t x) { return x << 1; }
```

clang output:
```asm
u8:
        and     x8, x0, #0xff
 lsl     x0, x8, #1
        ret

u16:
        and     x8, x0, #0xffff
 lsl     x0, x8, #1
        ret
```

GCC output:
```asm
u8:
 ubfiz   x0, x0, 1, 8
        ret
u16:
        ubfiz   x0, x0, 1, 16
 ret
```
</pre>
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