<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/117537>117537</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[SCEV] Assertion `isAvailableAtLoopEntry(Op, L) && "SCEVAddRecExpr operand is not available at loop entry!"' failed.
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
Nirhar
</td>
</tr>
</table>
<pre>
Faulty IR:
```
; ModuleID = 'test.ll'
source_filename = "/nfs/build-cache/zvm-dev-4598/jdk11/x86_64/fastdebug/lib/server/boilerplate.ll"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
target triple = "x86_64-unknown-linux-gnu"
define void @test(ptr addrspace(1) %p) {
entry:
%check = icmp eq ptr addrspace(1) %p, null
br label %bb0
bb0: ; preds = %loop0, %entry
br i1 %check, label %loop0, label %latch
latch: ; preds = %bb0
br i1 %check, label %exit0, label %loop0
exit0: ; preds = %latch
ret void
loop0: ; preds = %latch, %bb0
%0 = load atomic i32, ptr addrspace(1) %p unordered, align 8
%add = add i32 %0, 3
br i1 true, label %preheader, label %bb0
preheader: ; preds = %loop0
br label %loop1
loop1: ; preds = %backedge, %preheader
%iv1 = phi i32 [ %add, %preheader ], [ %1, %backedge ]
%1 = add i32 %iv1, -33
br label %loop2
backedge: ; preds = %loop2
br i1 true, label %exit1, label %loop1
loop2: ; preds = %loop2, %loop1
%iv0 = phi i32 [ %iv1, %loop1 ], [ %2, %loop2 ]
%2 = add nsw i32 %iv0, 1
%3 = icmp sgt i32 %2, 0
br i1 %3, label %backedge, label %loop2
exit1: ; preds = %backedge
ret void
}
```
fails when run with `opt -passes='print<scalar-evolution>,simple-loop-unswitch<nontrivial>' `
Demo of failure: https://godbolt.org/z/qhboK5r3j
</pre>
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