<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/117496>117496</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [MachinePipeliner] Pipeliner Doesn't Consider Phis in computeStart
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          mmarjieh
      </td>
    </tr>
</table>

<pre>
    When trying to schedule an instruction `X` and it has an input from instruction `Y` two iterations ago (fed by two phis), the pipeliner doesn't consider `Y` when calculating the EarlyStart and LateStart parameters.

For example:

%phi1 = phi ..., %y
%phi2 = phi ..., %1

%x = instruction_x(%phi2)
%y = instruction_y

When scheduling we have two cases:

1. instruction_x is scheduled before instruction_y, say at cycle x.
   Then the calculation should be as follows:
   `LateStart= min(LateStart, x + NumPhis * II - Latency_Of_x)`
  
2. instruction_y is scheduled before instruction_x, say at cycle y.
    Then the calculation should be as follows:
   `EarlyStart= max(EarlyStart, y - NumPhis * II + Latency_Of_x)`
   
   
 Reproducer:
 https://godbolt.org/z/r1c6bTd6v

II=7
Inst (16)   %11:gprc = ADDI %30:gprc_and_gprc_nor0, 4
is scheduled at cycle 10.
Whereas,
Inst (8)   %25:gprc = ADD4 %4:gprc, %23:gprc
is scheduled at cycle 4.
which is an invalid schedule.

Explanation:
Inst (8) needs the output of Inst(16) from 1 iteration ago.
This means that at cycle 4 + II = 11, Inst(16)'s output should be ready to use by the next ADD4.
Inst (16) only started at cycle 10 and has a latency of 2, this means that its output won't be ready at cycle 11.











 


</pre>
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