<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/117306>117306</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[x86][MC] Over-decode invalid instruction with mutual exclusive prefix and unmatch opcode
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
Mar3yZhang
</td>
</tr>
</table>
<pre>
### Work environment
| Questions | Answers
|------------------------------------------|--------------------
| OS/arch/bits | x86_64 Ubuntu 20.04
| Architecture | x86_64
| Source of Capstone | `git clone`, default on `master` branch.
| Version/git commit | llvm-20git, [f08278](https://github.com/llvm/llvm-project/commit/f082782c1b3ec98f50237ddfc92e6776013bf62f)
<!-- INCORRECT DISASSEMBLY BUGS -->
### minimum disassembler PoC program
```c
int main(int argc, char *argv[]){
/*
some input sanity check of hex string from argv
*/
// Initialize LLVM after input validation
LLVMInitializeAllTargetInfos();
LLVMInitializeAllTargets();
LLVMInitializeAllTargetMCs();
LLVMInitializeAllDisassemblers();
LLVMDisasmContextRef disasm = LLVMCreateDisasm("x86_64", NULL, 0, NULL, NULL);
if (!disasm) {
errx(1, "Error: LLVMCreateDisasm() failed.");
}
// Set disassembler options: print immediates as hex, use Intel syntax
if (!LLVMSetDisasmOptions(disasm, LLVMDisassembler_Option_PrintImmHex |
LLVMDisassembler_Option_AsmPrinterVariant)) {
errx(1, "Error: LLVMSetDisasmOptions() failed.");
}
char output_string[MAX_OUTPUT_LENGTH];
uint64_t address = 0;
size_t instr_len = LLVMDisasmInstruction(disasm, raw_bytes, bytes_len, address,
output_string, sizeof(output_string));
if (instr_len > 0) {
printf("%s\n", output_string);
} else {
printf("Error: Unable to disassemble the input bytes.\n");
}
}
```
### Instruction bytes giving faulty results
```
f2 f0 41 0f b7 d6
```
### Expected results
It should be:
```
Error: Unable to disassemble the input bytes.
```
### Actually results
```sh
$./min_llvm_disassembler "f2f0410fb7d6"
xacquire
```
<!-- ADDITIONAL CONTEXT -->
### Additional Logs, screenshots, source code, configuration dump, ...
This is similar to [a verified bug](https://github.com/capstone-engine/capstone/issues/2547) in the capstone engine. Bytes "f2f0410fb7d6" can not be translated into valid x86 instructions because of mutual exclusive prefixes `f2`, `f0` and LOCK prefix on register operation. But llvm MC accepts it into instruction `xacquire`. All the other instruction decoders like the Capstone, Zydis, and Xed reject the byte sequences. Not sure whether the workaround in this [pull request](https://github.com/llvm/llvm-project/pull/117299) can fix this.
</pre>
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