<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/117098>117098</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISC-V] Don't support fixed vector types in inline asm
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          zengdage
      </td>
    </tr>
</table>

<pre>
    If use fixed vector types to be parameters in inline asm for risc-v,  I'll get the error information, 
`error: couldn't allocate output register for constraint 'vr'`

The test code as follows:
```
#include <riscv_vector.h>

#define RVV_FIXED_TYPE_DEF(name, lmul) \
  typedef vint8##name##_t fixed_vint8##name##_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen * lmul)));

RVV_FIXED_TYPE_DEF(m1, 1);

fixed_vint8m1_t test(fixed_vint8m1_t lhs, fixed_vint8m1_t rhs, fixed_vint8m1_t acc) {
 __asm__ volatile("vmacc.vv %0, %1, %2\n\t":"=&vr"(acc): "vr"(lhs), "vr"(rhs), "0"(acc): "memory");
  return acc;
}
```
Build command: `clang test.c -o test.S -march=rv64gcv -mrvv-vector-bits=256`



</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJx0VFGPozYQ_jWTl1EiGEIgDzzshY20b9XdadU-IWMG4srYkW24bn99heH2tttUQraZsb-Z7_N4hPdqMMwV5F8gr3diCjfrqr_ZDJ0YeNfa7q166XHyjL36izucWQbrMLzd2WOw2DLehRMjB3YelUFltDKMwo_YW4dOebmfgS6IL0CF1jhwwHBjZOesQ2V660YRlDXLJkhqSJ7glEQvZE8o7aQ7A1QEFFpbKQKjncJ9Cuh4UD6wi4GkNT44oUxAoGJ2QAWckg0vjt9vjIF9QGm7JUHsrdb2h4fs6T3s9q2_lCkj9dQxQnZZiMzNSv9wg-z5IzRQ1nG_8P76-tpcX35_rpvvf_z23NTPV6DSiJEXdnqcNNAZIb-s5zAK2XGPszKhBMqAsnX3smrCqnrzf96mESE41U6BmwaoBCrXPN38M9emVcEDlU2zMWg2SM0GgZ5-JrV92ZePvB6yGdOFS_rf3R9yHdMmRLGBys9mffMLwGeze2wWUkbJii3UwtmPTYOz1SIozZE2zaOQ8jDPCJQnsZIoT7eZIL8YyC8BiJbLXsYa6LQUCQGVa4il2BagzRizPK8I70b30Zg8OD3yaN1bdPxSB9FxmJyJXN4lK-qHVfdlUrpDacdRmC6inhKphRminAeJe7uuvuF-FE7eIKvdfDoOcsb96OZ5v977Pt57VlN--vQO1nHXVVl3zs5ix1VaZJTmxzJNdrfq3KZF352LXIi84_5YFOey5TIpe8GJPB13qqKEjmlKaULJKU8OLI5t31NHJ5kfkzSDY8KjUPqg9TwerBt2yvuJqzQtknO506Jl7WPLITL8A6N30Syvd65aDu3bafBwTLTywf-CCSro2Ku-vny77F8hr7G2a2_w0_1uXXjUpf7VlHaT09UthHt89nQFug4q3Kb2IO0IdF1ibdP-7uyfLAPQNWboga4bhbmifwIAAP__skmVkg">