<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/115697>115697</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Missed optimisation to take advantage of commutative SVE fmul instruction
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          ktkachov
      </td>
    </tr>
</table>

<pre>
    Example AArch64 SVE intrinsics code:
```
#include <arm_sve.h>

svfloat64_t svmul_x_2(svfloat64_t x, svfloat64_t y, svbool_t pg)
{
    return svmul_x(pg, svdup_f64(2), x);
}
```
This can generate just a singly FMUL instruction but LLVM moves the immediate 2 into a register first.
https://godbolt.org/z/11aEEGoce
</pre>
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