<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/115640>115640</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Why does llc compile direct calls to RISCV interrupts?
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          workingjubilee
      </td>
    </tr>
</table>

<pre>
    The following code compiles:

```llvm
source_filename = "example.925e6eb0586113f0-cgu.0"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
target triple = "riscv64-unknown-linux-gnu"

define void @_ZN7example17interrupt_machine17h9aedfc539b69d0e4E() unnamed_addr #0 {
 ret void
}

define void @_ZN7example20interrupt_supervisor17h3af0168b331d21a0E() unnamed_addr #1 {
  ret void
}

define void @_ZN7example4main17h90b0fda4f240e4d2E() unnamed_addr #2 {
  call void @_ZN7example17interrupt_machine17h9aedfc539b69d0e4E() #3
  call void @_ZN7example20interrupt_supervisor17h3af0168b331d21a0E() #3
  ret void
}

attributes #0 = { nounwind uwtable "interrupt"="machine" "target-cpu"="generic-rv64" "target-features"="+m,+a,+f,+d,+c" }
attributes #1 = { nounwind uwtable "interrupt"="supervisor" "target-cpu"="generic-rv64" "target-features"="+m,+a,+f,+d,+c" }
attributes #2 = { uwtable "target-cpu"="generic-rv64" "target-features"="+m,+a,+f,+d,+c" }
attributes #3 = { nounwind }

!llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3}

!0 = !{i32 8, !"PIC Level", i32 2}
!1 = !{i32 1, !"Code Model", i32 3}
!2 = !{i32 1, !"target-abi", !"lp64d"}
!3 = !{!"rustc version 1.84.0-nightly (b91a3a056 2024-11-07)"}
```

It seems like it should not, given that this code does not compile:
```llvm
source_filename = "example.925e6eb0586113f0-cgu.0"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

define x86_intrcc void @_ZN7example13lol_interrupt17h978ba38488afd6e7E() unnamed_addr #0 {
  ret void
}

define void @_ZN7example4main17h90b0fda4f240e4d2E() unnamed_addr #1 {
  call x86_intrcc void @_ZN7example13lol_interrupt17h978ba38488afd6e7E() #2
  ret void
}

attributes #0 = { nounwind nonlazybind uwtable "probe-stack"="inline-asm" "target-cpu"="x86-64" }
attributes #1 = { nonlazybind uwtable "probe-stack"="inline-asm" "target-cpu"="x86-64" }
attributes #2 = { nounwind }

!llvm.module.flags = !{!0, !1}
!llvm.ident = !{!2}

!0 = !{i32 8, !"PIC Level", i32 2}
!1 = !{i32 2, !"RtLibUseGOT", i32 1}
!2 = !{!"rustc version 1.84.0-nightly (b91a3a056 2024-11-07)"}
```

Of course, x86 is uniquely "quirky", especially on interrupt entry. I'm not aware if this is... conceptually valid? ...for RISCV, so feel free to close this if this is truly intentional.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzEV1mP2zga_DX0CyGBhyzJD37oY3vRQHazSLIzwLw0KPKTzTRFOjzs9vz6gQ5fnelJZyYHYIgWxfq-YpmugkQIemUBlmh-jea3M5Hi2vnlzvlHbVcfU6MNwKxxar_8sAbcOmPcTtsVlk4Blq7baAMB8StEbhE5XEsyfozZduNUcMlLeGi1ASs6wIjfYsQYPIluYyBfsDmU0JB5XVLKW5LJVcoJYmxER-FXELESURixdyke8VmH-BVkG8SvymK4ZPr4hbIa8SvK6sxyNs697-eelY1eb8yRktdBbssiS_bRup3NjLbpKVvZdISNVwWttoC3TiuMCvLw23-raTe00jaC92kTHzoh19oCrdYLAaqVc75oyoUiUPwL9UwWONleEPUglPIYMU4wqq7HFthDHBpMfavb1xFg5EQgpA34rQ7O02rNRUtoWTecU8WoIC9xoGcc_i6JohPa9vsmDWmVKFpWECgUe6knO-8phTH_XFrEOP9Sxa_W6rzoX0ojYvS6SRHC9LP256u6xtYlu9NW4bSLoukPHmNHDv0h47eIsWl3iLH--XhSM7lJxwUrsOC1zPy2LC5XtSBi8hCOSxG77hC7QexajEM7Dmoc5AA_kL-kTb-S9knCn82cHZmfEf5pbPjnOj47LojR3i7zzqlkIG-NWIXJk2j_z2CUIHbT39FpZKcKE1YrsPESxD9vQ85WaM5wPdVDjP3v_ga_gS2YYbc3uH980YY-w9IT9qZPhP84dQHm52D2MniSXDR6Ao_TZlMWqp85q8IvN9hbdgpR4i34oJ3FNK-LnGRWr9bR7DFidbOgggsyLzEjrMgozUiF2OKi7iGyzrW6jzgAdAEb_QhYRxzWLhmFrYs9xZXegsVxLSKOax3GSFQOQr_gkI2naPzxocgqgvjVEH2c9bf08pZ9ITXbmhzyc5gqD_BXBelTXT68Pkf71dpGL-Wf-j43zjwc7ab3_KpuBK-LuhatKqF6TZz-qCijn0XZt9pd72vfJnyss0b8vm-eOfrGuwayEIV8PNqetkZbyEToXvb0p7rMJv_8cpD82M7sm1rvKyyXfV_LPbPHd_GNbv4f4N9vP5yh6Uue-33d8m2LpUs-QM_jqS6xDjhZ_SnBUJd9Sto_7ieeEDYgtTBmj53Fx6OPwUa_z_E9YlU32KjYCQ9Yt6PF6pDnOZbOStjENMC3wmiF-B3O87x1Hr-7f3_zS98iONwCGNx6ABwdlsYFmMocy-Hok9kPBGzUzgqTz9SSqwVfiBksacUpY0VV0tl6KRVQPm_VoiFKCqFaUbVy0fKqIbxpOZnpZa8YpZSQqigJzau5VGrezOW8JooVNSoIdEKbfDg6zq9mOoQES0rnZUFmRjRgwvAqxpiFHR6e9orNb2d-2YOyJq0CKojRIYZTmaijgeWv6_2YP8bIQ_5gpT3IONhQ6GUY9DkpHhC_myVvlusYN8OLHLtD7G6l4zo1uXQdYndDYo1DtvHuI8iI2N1ALiB2N7HfLtkfAQAA__8-CRms">