<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/114359>114359</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [InstCombine] increased undefinedness when folding `(or (and (bitcast F) INTMAX), INTMIN)`
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          bongjunj
      </td>
    </tr>
</table>

<pre>
    ```llvm
----------------------------------------
define float @fneg_fabs_fabs_as_int_f32_and_or.2(float %val) {
#0:
  %bitcast = bitcast float %val to i32
  %and = and i32 %bitcast, 2147483647
  %or = or i32 %and, 2147483648
  %fneg.fabs = bitcast i32 %or to float
  %#1 = fmul float %fneg.fabs, %fneg.fabs
  ret float %#1
}
=>
define float @fneg_fabs_fabs_as_int_f32_and_or.2(float %val) {
#0:
  %#1 = fmul float %val, %val
  ret float %#1
}
Transformation doesn't verify!

ERROR: Value mismatch

Example:
float %val = undef

Source:
i32 %bitcast = #x00000000 (0)   [based on undef value]
i32 %and = #x00000000 (0)
i32 %or = #x80000000 (2147483648, -2147483648)
float %fneg.fabs = #x80000000 (-0.0)
float %#1 = #x00000000 (+0.0)   [based on undef value]

Target:
float %#1 = #x80000000 (-0.0)
Source value: #x00000000 (+0.0)
Target value: #x80000000 (-0.0)

Summary:
  0 correct transformations
  1 incorrect transformations
  0 failed-to-prove transformations
  0 Alive2 errors
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy8Vc9vozgY_WvMxUpkPkOAA4f8mEg97KzUHa32FhmwE1fGrmyTmf73KxuSQrvR9jSoAty89_w-f8-YOSfPmvMa5TuUHxI2-IuxdWP0-WXQL0ljurcabcj4p9S1R-SAyHb1xWtEd1xIzbFQhnmMMiI0P58Ea9x4Y-4ktT8JCiemu5Oxa0BQTmjIr0whqDAqdqMaAkoQ3Y4DHBCN9C1zHiN6wLf3OR17gyWFGYPpLqLDU1KYiSDYY0izIivpJitmFGMjw9gbgeluAS5n4FDhOhS38DQRjQ2GosEZBQFNI1r0g3q3f1cKcy3GE9XyWbFBZFql4jC90AOi335PIx7UEIn729sXff-wTDthbM-8NBp3hjuNoPD4yq0UbwhuhHj_9vz85zOiW_w3UwPHvXQ98-1lAfnF-lfF744XCQmmB91xMWf8ZQbbvhOWQYkUBPQXmS6MoCRhgTBG-a5hjnfY6FEVX4MtlB8WSrcU_pfKAjhlL-DKGW4WPdjj1XxYfahxGciPQiuyJp85925-9IdgNxK-UOrUTGbP3H9e-sUUDx2NfZiE6faxn_lkS_hD7WmGoe-ZfZulmeDWWMtbj_0iiPd9l2Kp_wdCsGBS8W7lzerVmit_DNwqeeWAubXGTv--f3aTrqZdRSuW8DotKKF5uinS5FKTKutEsaHQlaJNKyZoxgvSbPKyLURFi0TWQCBLCU1JnmY0XQPpNpsybaqCCWjKBmWE90yqdfi0r409J9K5gddpmtG8ShRruHLxcADQ_CeOvyKAcFbYOpBWzXB2KCNKOu_eZbz0Kp4qT9r5vekbqUMmwppZHvMSwyI17zR3Dv-8cI2FUZ3UZxzKhjKEHsq4R6C8bbpjSN3T9x9_bP8JLYR9HDx9D4MNSQar6ov3ry50Eo4IjmfpL0Ozbk2P4BgPsPERGvLCW4_gGItyCI5T1dca_g0AAP__onj4hA">