<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/113941>113941</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [llvm-exegesis] Check PFM counter mappings for AlderLake/SapphireRapids
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            tools:llvm-exegesis,
            backend:X86 Scheduler Models
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            boomanaiden154
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          boomanaiden154
      </td>
    </tr>
</table>

<pre>
    There seem to be some conflicts between different documentation sources (primarily a section of the Intel architecture manual on Golden Cove and seemingly most other things) regarding which counters are grouped. Libpfm/others have performance counters for ports 2/3/10 on golden cove based CPUs, whereas that section of the architecture manual has ports 2/3/11 grouped.

This should be investigated and either fixed in LLVM/libpfm if it is an issue there, or feedback should be sent to Intel to fix their documentation.
</pre>
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