<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/112271>112271</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            GlobalISel generator gives an obscure error when setting incorrect defs on an instruction that modifies physical registers
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          JL2210
      </td>
    </tr>
</table>

<pre>
    Repro (run from build tree one level under project):

```
include "llvm/Target/Target.td"

def T : Target;

def A : Register<"">;
def B : Register<"">;

def R1 : RegisterClass<"", [i1], 0, (add B)>;
def R8 : RegisterClass<"", [i8], 0, (add A)>;

def FOO1 : Instruction {
  let OutOperandList = (outs);
  let InOperandList = (ins);
  let Pattern = [(set A, (add A, 1))];
}

let Defs = [B] in
def FOO2 : Instruction {
  let OutOperandList = (outs);
  let InOperandList = (ins);
  let Pattern = [(set A, (add A, 1))];
}
```

command:
```
./bin/llvm-tblgen -gen-global-isel -I ../llvm/include ./test.td
```

log:
```
Type set is empty for each HW mode:
possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
FOO2:   (FOO2:{ *:[i1] })
// record omitted for brevity
./test.td:18:5: error: Type set is empty for each HW mode in 'FOO2'
def FOO2 : Instruction {
 ^
```
</pre>
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