<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/111642>111642</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            RVV instruction still generated even when auto vectorization are totally disabled
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          fanghuaqi
      </td>
    </tr>
</table>

<pre>
    Hello there, I met a strange issue when using LLVM/Clang to build c code with RISC-V Vector extension enabled, see test code here https://godbolt.org/z/GreE5bTWo

I am expecting when passing `-O2 -march=rv64imafdc_zfh_zvfh_zve64f -mabi=lp64d  -fno-vectorize -fno-slp-vectorize` compiler options, auto vectorization will be totally disabled for RISC-V, but I can still see many RVV instructions generated such as `vsetivli` and `vle64`.


Is above behavior expected? If yes, If I want to fully disable any vector instruction generated, how to achieve it.

Thanks
Huaqi
</pre>
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