<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/111205>111205</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [amdgpu] some VOP3 instructions not defined as commutable
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          yxsamliu
      </td>
    </tr>
</table>

<pre>
    some VOP3 instructions are commutable but are not defined as such. e.g.

```
# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=machine-cse -verify-machineinstrs %s -o - 2>&1 | FileCheck --check-prefix=GCN %s
---
name: test_machine_cse_op_sel
body: |
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    %1:vgpr_32 = IMPLICIT_DEF
    %2:vgpr_32 = V_ADD_NC_U16_e64 0, %0, 0, %1, 0, 0, implicit $mode, implicit $exec
 %3:vgpr_32 = V_ADD_NC_U16_e64 0, %1, 0, %0, 0, 0, implicit $mode, implicit $exec
    DS_WRITE2_B32_gfx9 undef %4:vgpr_32, %2, %3, 0, 1, 0, implicit $exec
...
```

V_ADD_NC_U16_e64 is commutable but are not merged by machine-cse.

This issue was found during reviewing https://github.com/llvm/llvm-project/pull/106920

Two changes are needed:

1. td files need to be updated for commutable VOP3 insts
2. SIInstrInfo::commuteInstructionImpl need to be fixed to handle op_sel
</pre>
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