<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/111046>111046</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [x86-64] Work done in vectors shouldn't round-trip to general-purpose registers just to do one subtraction (`bitReverse(bitReverse(a) - bitReverse(b))`)
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Validark
      </td>
    </tr>
</table>

<pre>
    This code: ([Godbolt link](https://zig.godbolt.org/#z:OYLghAFBqd5QCxAYwPYBMCmBRdBLAF1QCcAaPECAMzwBtMA7AQwFtMQByARg9KtQYEAysib0QXAMx8BBAKoBnTAAUAHpwAMvAFYhptJg1AAvPMFJL6yAngGVG6AMKpaAVxYMQADlIOAMngMmABy7gBGmMQgAOykAA6oCoS2DM5uHt7xickCAUGhLBFRsZaY1ilCBEzEBGnunj6l5QKV1QR5IeGRMRZVNXUZjX3tgZ2F3dEAlBaorsTI7BxoDAoEANSr6GsApJIAImsAAngsCTUQ2wBMl5tXl5O7AELbGgCCL6%2BYqmfrVAxr/FQEHUa1cADYACykNYATxAoMhkwREJ20WebzWmLWxEwBDm/0OYUIACVMAA3SJKCCEknkymYYFIgC0VwArEciQRSRTiFSYZMHpJ0e9onsPh8vj8Af8wtVgfDwVDYQrEcjUcKsWtlqs1kwVSjdgdOdz6ZdGU8Pprteswvqdvs1sa6bzMGb%2BRaMVicXjiDLaTylFwIGS4gpXGEAI4QJjQsICj0isVvD5/R1MYzy5HQuHIpGK9WWrHWtYU5D2o3%2B%2BmSCAAOm2aLWqmzqL2go1Xtx%2BMdlZdQdL21Zjw0A4OLMu7P7g64I7bhcxAHp596u4SYQRMEIAO5MOLUpgKC6Dy4jxXQmm1fcEalOgMMw776kANTKRGIEC4YOhri80w5hEcl7RmsY7snGAoPIOw6sq2s7JqK4pvKmN70kGIKKnmkIFp6mLLr6HJrhu267veB6nn%2BF6rNePZUiRT4viQEA%2BKCP5npyAGUao4HgQm9ZJu8iF%2BlyzpKGaaGqvm9btjhnZ4ee7FXueJounuB6HM%2B1gMUx36/nJgGruuW47oyXE8fByYCd2Qm3tWIJqfRb6XF%2BiJIgOjzHtBElonO2IyQSbF6chym0XZGlvh%2BX4seR8nXgRhm7pxJlCuKZn8a8qYhmGkbRvqsb6hhBpedhPk%2Bv80YKCwawXNcGXhhGOzjq5YQjtCbKuUwzX1ayrneiOdzeZq8LdbiI71ce%2BxknclUspI2BHOpr4QI5ubTP1WKDYO7XQaNE3XJVTArUVmqYo1I13DtlyVXGpDefGkG9UlcF8R8i5IQoRHZbmaqSc986amS1Q%2BWGtAEHahq6gmi6avuFVVZcYRvTunVDUDBC9dcP1HWtOyDjiKOnejlyPMQk0QLjrjAwdryQ5jayDW81OYrBVO/R2JWA%2BTqMPczvEfBw0y0JwrK8J43C8KgnAAFpmBsszzJg9WSJIvAgxwWgCqQCCYEwWBRBA0wANYgKyGg1hClwAJxm5cEIQlwZvm9ErKkALHAQrwLASBoGikCLWikOLHC8AoIDeyraukHAsBIGgpx0JE5CUDHcRx1ExgEMQrgMPrfB0OuvKULaqu8ESzDEHCoukCX1QwgA8mE2gvpwPCkDHbCCDXDC0OXftYGErjAABtC0MHFdYCwhjAOIRekPgOLlBSI9%2B18ZSuOuTe8IE64u37tB4GExDV84WCaMrxAnOvpA8mEiSYHsmDj0Yu9GCf0xUAYwAKI%2BeCYJuNdxIwF9%2BCCBEGIdgdsZCCEUCodQ09dBcGdhPEAphzC73hvAaYqA4g2AECPJkNc1iknoPuTAAAxS8wE%2BjAFxI2LwYIAD6kImRP1cKoYCLBkBxFcIaYwDAeRu39jyM%2BWBg6QGmE0bBngIAOAGJ4eB/hRgFCKBILISQJEyOUQkVRKQOiKO6PA8RFRhjqP0ZgKwEjWg1B0V0KI%2BijEuHqMo1YbQrHjBsWI2WCw9D80FsLE%2B/tOBrGQWsdOmd9aVVwIQEgCtJCTGVi/aYmttbdD1qQQ2EJzY1lZNEDQWTHasi8FkjQlxPwu34R7LgXsfZ%2BIDkHEOpAw5828RwS4vjp41PqfEy%2BlIUggAhEAA%3D))

```zig
export fn foo(x: u64, y: u64) u64 {
    return @bitReverse(@bitReverse(x) -% @bitReverse(y));
}
```

LLVM version:

```llvm
define dso_local i64 @foo(i64 %0, i64 %1) local_unnamed_addr {
Entry:
  %2 = tail call i64 @llvm.bitreverse.i64(i64 %0)
  %3 = tail call i64 @llvm.bitreverse.i64(i64 %1)
  %4 = sub i64 %2, %3
  %5 = tail call i64 @llvm.bitreverse.i64(i64 %4)
  ret i64 %5
}

declare i64 @llvm.bitreverse.i64(i64) #1
```

Compiled for Zen 4, we get:

```asm
.LCPI0_0:
        .byte   1
        .byte   2
 .byte   4
        .byte   8
        .byte   16
        .byte 32
        .byte   64
        .byte   128
foo:
 vpbroadcastq    xmm1, qword ptr [rip + .LCPI0_0]
        vmovq   xmm0, rdi
        vgf2p8affineqb  xmm0, xmm0, xmm1, 0
        vmovq   rax, xmm0
        vmovq   xmm0, rsi
        vgf2p8affineqb  xmm0, xmm0, xmm1, 0
        bswap   rax
        vmovq   rcx, xmm0
        bswap rcx
        sub     rax, rcx
        vmovq   xmm0, rax
 vgf2p8affineqb  xmm0, xmm0, xmm1, 0
        vmovq   rax, xmm0
 bswap   rax
        ret
```

This is pretty inefficient, given that we can avoid the round-trip to scalar registers by using a vector subtraction and hoisting the bswaps such that they are done before moving to vector registers. Here is what I would expect:

```asm
.LCPI0_0:
 .byte   1
        .byte   2
        .byte   4
        .byte 8
        .byte   16
        .byte   32
        .byte   64
 .byte   128
foo:
        vpbroadcastq    xmm1, qword ptr [rip + .LCPI0_0]
        bswap   rdi
        bswap   rsi
        vmovq xmm0, rdi
        vmovq   xmm2, rsi
        vgf2p8affineqb  xmm0, xmm0, xmm1, 0
        vgf2p8affineqb  xmm2, xmm2, xmm1, 0
        vpsubq xmm0, xmm0, xmm2
        vgf2p8affineqb  xmm0, xmm0, xmm1, 0
 vmovq   rax, xmm0
        bswap   rax
        ret
```

Same principle applies to earlier targets like Zen 3. Currently, Zen 3 attempts to do a SWAR implementation. Doing a vector implementation is much faster. Here is what I would expect: [Godbolt link](https://zig.godbolt.org/#z:OYLghAFBqd5QCxAYwPYBMCmBRdBLAF1QCcAaPECAMzwBtMA7AQwFtMQByARg9KtQYEAysib0QXAMx8BBAKoBnTAAUAHpwAMvAFYhptJg1AAvPMFJL6yAngGVG6AMKpaAVxYMQADlIOAMngMmABy7gBGmMQS0gAOqAqEtgzObh7epHEJNgIBQaEsEVFSFphW2QxCBEzEBCnunlwlZUmV1QS5IeGR0RZVNXVpjQp97YGdBd1SAJQWqK7EyOwcaAzDANTD6GsApJIAImsAAngscTUQ2wBMl5tXl1O7AELbGgCCL6%2BYqmcEa1QMf1QqAg6jWrgAbAAWUhrACeIDBUKmiMhOwA7M83mtsWtiJgCPMAYcwoQAEqYABukSUEGJZMp1MwIORAForgBWI4kgjkqnEGmwqYPSSY95ovYfD7/NZhaoghEQ6FwhVIlHo0U4tYrdZMFWo3YHbm8xmXZlPD6a7W/MJ6nb7GX0vlKU2C81YnF4gnEAFGhn8zBcCAUmIKVxhACOECYMLCQrdYolbw%2BXx%2Bfx9TGM8pRMPhKORivVFpxVrWVOQdsNjsZkggADpthi1qoc%2Bi9sKNR78YSHTy/UpA2XtuzHhohwc2ZdOYPh1wx%2B2i9iAPSLz3d4mwgiYIQAdyYMVpTAUF2HlzHiphdNqh4ItN9TqZh0PtIAaphrCQIFxwTDXF4ZlzCEca8ozWCdOVjIUHmHUd2Tbeck3FSU3mlO9GUDUFFXzKFC3dbFV29LkNy3Xd90fI9zwAq9hlvKt/QPI9Dlfd9iAgHwwT/C9uSA6jVEgyD4wbRN3mQn1aOdLNMLVBsOzwrsCMvbib0vY06LIl83yIFi2N/f8FOA9dNx3PdmT4gTEKTESexUpQa1BRiNI/S4fyRZEh0eU9YILaSF1xOSiS4/TUNUp97OYz9v3Y3SAuogziOM3jTJFSVzOE15pWDUMIyjPUYz1LD9QxHz8IBKMFBYNYLmuDKw3DHZJzcsIxxhDk3KYJq6vZNzPTHO4fM1BEuvxMc6tPfYKTuCq2UkbAjiYzSICcvMZj6nEBuHNrYJG8brgqphltwzUcQa4a7m2y4KtjUgfLjaCeqShChI%2BZcUIUEjsrzKTCreZdNQpapfNDWgCFtA01ja%2B7Xh%2BnFD3KyrLjCV69w6wbAYIHrriexdDtWnZhzxVGToxy5HmICaIHx1wgf2yGsextYBu%2B2nsXgmnNWKgHKbRiHl0Ej4OBmWhOHZXhPG4XhUE4AAtMwNjmBZMDqyRJF4YGOC0IVSAQTAmCwKIIBmABrEB2Q0WtIUuABOc3LkhSEuHNi20XZUhBY4SFeBYCQNA0UhRa0UgJY4XgFBAH3VfV0g4FgJA0FOOhInIShY5ieOomMAhiFcBgDb4OhN35SgbTV3gSWYYh4TF0hS%2BqWEAHkwm0DTOB4UhY7YQRa4YWgK/9rAwlcYAgNoWgQ8rrAWEMYBxGL0h8Dxaw8CpUf/a%2BN9XE3ZveECTdXf92g8DCYga%2BcLBNBV4gTk30g%2BTCeJMD2TAJ6MfejDPmYqAMYAFGfPBMG3WuYiMCvvwQQIgxDsHtjIQQigVDqBnroRoBhX6mHMPvBG8AZioBiOUUeLJa5rHJPQQ8mAABi15QJ9GAPiJsXhwQAH0oQshfq4VQoEWDIBiK4A0xgGB8mVgHPkF8sAh0gDMSwGkkj2AYE4Fw9QQCXGkP4MY%2BRCjG2/JkRIAgBgNDRBkeImiGAdBUd0b84iF4CFaP0WRaQFFNAkRYkYRiuhRHZKYkY2iJC6OGG0JxEwojgjEXLRYegBZCxFmfAOnA1goLWBnLOBsKq4EICQRWkgpgqzfjMLWOtuj61IEbSEFtazsjRBoEpTt2ReBKRoS435Xbu1IJ7Lg3tfYRMDsHUOpBw781CRwS44SZ7tK6Zk6%2B1JJGQiAA%3D%3D%3D)

```asm
.LCPI0_0:
 .byte   7
        .byte   6
        .byte   5
        .byte 4
        .byte   3
        .byte   2
        .byte   1
 .byte   0
        .byte   15
        .byte   14
        .byte 13
        .byte   12
        .byte   11
        .byte   10
 .byte   9
        .byte   8
        .zero   16,15
.LCPI0_2:
 .byte   0
        .byte   128
        .byte   64
        .byte 192
        .byte   32
        .byte   160
        .byte   96
 .byte   224
        .byte   16
        .byte   144
        .byte 80
        .byte   208
        .byte   48
        .byte   176
 .byte   112
        .byte   240
.LCPI0_3:
        .byte 0
        .byte   8
        .byte   4
        .byte   12
 .byte   2
        .byte   10
        .byte   6
        .byte 14
        .byte   1
        .byte   9
        .byte   5
 .byte   13
        .byte   3
        .byte   11
        .byte 7
        .byte   15
.LCPI0_4:
        .byte   15
baz:
 vmovq   xmm0, rsi
        vmovq   xmm1, rdi
        vpbroadcastb xmm5, byte ptr [rip + .LCPI0_4]
        vmovdqa xmm3, xmmword ptr [rip + .LCPI0_2]
        vmovdqa xmm4, xmmword ptr [rip + .LCPI0_3]
 vpunpcklqdq     xmm0, xmm1, xmm0
        vpshufb xmm0, xmm0, xmmword ptr [rip + .LCPI0_0]
        vpand   xmm2, xmm0, xmm5
        vpsrlw  xmm0, xmm0, 4
        vpand   xmm0, xmm0, xmm5
        vpshufb xmm2, xmm3, xmm2
        vpshufb xmm0, xmm4, xmm0
        vpor    xmm0, xmm2, xmm0
        vpshufd xmm2, xmm0, 238
        vpsubq  xmm0, xmm0, xmm2
        vpand   xmm2, xmm0, xmm5
        vpsrlw  xmm0, xmm0, 4
 vpand   xmm0, xmm0, xmm5
        vpshufb xmm2, xmm3, xmm2
 vpshufb xmm0, xmm4, xmm0
        vpor    xmm0, xmm2, xmm0
 vmovq   rax, xmm0
        bswap   rax
        ret
```

Note: We interleave `xmm0` and `xmm1` so we can operate on both inputs in a single a vector. 

</pre>
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qOvVBpHD2bN0oVcco-GmFUPw1mRTlH1aDRp9yp8_SMR6LZvpN5Tp-9vHYNM_OJuvXhyUPx5efjT8oqsm_6dTP_HOLvwF2YcWYBjxoRHECxuIV0a86FQI_J117D9DKW5xVz-7FMB_tfxtKcCvS_HKZfCi-fkYziDYF8696okI-oViln5nIACvAJQX6UJQHzdzLxQC_IWn1Kv2b_XeROLV0gIK_yn-5Aug6oVprwz7Q379KelfaPswnB-n-Mvu-kWKLt8H7EWJvKqcD7W92ETepTz1Ght8Iwz82w_42x8BrO8ExMeN8vf-PbhTLe9UD5Uf9-7Uh-hd1Pp3ZvKtB_1N7w9-x0_9mZ_8zn9pxqoJ86KNHsjDLz3yB3hf0yfjOfioq_7fAMvGryLsp-7_q5zlLxq7Yvq1j6deCnxv2K8Cv7rwVTX5Akr41VnqVVjq7l0Awe8CGP3iOCCZDwGPf4J4_Gex_E-D-J9G7_8VSrOth8djNm6MpdUQd0XsX2JsQeMPDTT-gD-fl8T9sq-_wqt1E3f-EGN1hQX1kGBp1YxDj6UV5mN9WqEi_obGfMaeyj5FX8iIJVn_U_yFWIEVy9z_PyVfQOzHgCH8FUkuKQYQfuwHMb2iljgLztQy_JR-ATigCBwnCZYgCeZzQOPEmYoBDc40zUSrBYXHpZ8Wnx-3ZuoOfUr7foy_EASBU_Snwg_ion88dQRAFU_YY3YB7nvJp-7LnemvYET9gsKLtB_672KGdCgejyvNDP0Xfd-7MLfu8ifWm1ZvHvZYn9RjEVULsBre4c0oruLOL_5qxq6p-_gH4Dkb--EN1bpL-xF1XgBmQf98Q_GnC_9x3xH7meDtjiONLwD7aeyKLz9DVigdkjH4HNblAkiPm4nPj7-ars7i8N6fP8LSL4D0FrfLF_B_AgAA___DDQkV">