<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/110875>110875</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AVX2] vectorized `a == (a & b)` should not be switched to `0 != (a & b)` when it doesn't help
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Validark
      </td>
    </tr>
</table>

<pre>
    In trying to work around https://github.com/llvm/llvm-project/issues/110868, I wrote this code:

[LLVM Godbolt](https://llvm.godbolt.org/#z:OYLghAFBqd5QCxAYwPYBMCmBRdBLAF1QCcAaPECAMzwBtMA7AQwFtMQByARg9KtQYEAysib0QXACx8BBAKoBnTAAUAHpwAMvAFYTStJg1C1aANxakl9ZATwDKjdAGFUtAK4sGexwBk8DTAA5DwAjTGIJAGZSAAdUBUI7Bhd3Tz04hNsBPwDgljCIrmirTBskoQImYgIUjy8uS0xrLIYKqoIcoNDwvQVK6tq0hr72zryCiQBKS1Q3YmR2DiwaAIBqdAVUAH1aVFFaVYBSSKcANklV1VW8AA5j7FWAARCqiGOnSIAmS%2Bu7yIfDp8AKwaUhHE5fH63e5HYENa7nWFAz6TVa7fZbNwMZhsdBbJjodDEI4AdgAQocNABBbCCYgATxAlKpqyRkXBABFVgoEG4qFR6KZSkRie9IVdof8kaDwR9vhK/gC4WD3oiJV8Ye88JCZdrvvC9atPmDDdFrpDpObvkCTZDTrbviSHasbs6AJzOri6yFcA0%2B41W1ZFT2Ww1cG2Brj2yNOyOuyMewOfb3fT5%2B1MBw2fM1Z0OQ4HOz7RrOxrPxrOJ00p1aRdM1zOQyI5xt576RCOm4uN0uN8uNysW6uSOuSBvfSTN8et1aSDsWrvjnvjvvjgfW6tAuvI51AyerIHToFz60L/dL/cr/dr1anaunOunMc3yL3ZmswEHznXBhKapNTBsIIspcFC5wwnEeCbAwJqIh%2BmaIhob5IkCX48nyAqYEKNgkMBoGSJqwKWu8IESmBUoQVBKonDcUIalKWo6s6FECM61bMdBgZsagkEsZxTHcVBr7Uu%2BwKnF%2BISEKIfSyjRpH4fRwIoUQspqr8QkskiJKoby/KCsKOGqhcCoEUC0aGVCiqrOxVFnEZVqaichrVs5rGuXx7lOZ6XmRt5Ya%2BT6/n6peXDBaFnphXG4WeteXAxXF0UJQmiWds6kSnmlqXpVlmU5YGkTnvlqUFcVRWlXl54Hjuh7VVVtWBpV9WHse%2B7NUeO6tR17XtepIlAjRxxcoY6AqXZkpKkCsZajRBo0ZmNGhjR5bTcWNFfCaNHnOtqwALRcJ8S1Bltc0zltB1Rlta2/DeC07XtZ1HVtN1nSt9ZbZtV27ftW0zUaj2nd9L2Xbc11bZ991XcdT0Axdx3vcDYPfQ9V1Q1d51XUDG03QjqNI8DKPA2jwMYyDH13YjEN/Vdz0w29WN3T1SIAHQMKgBBfngyAsDEqyYAAjiNFkmfGABe4TcQwiRiHgovEEhH5uqh/42ALEpcCZzOszZqljWyWujZZU1Grqs3G0bR2m8m5tWxDFu29bwOWzb9sm87ZtO%2B7Dt2x7Lve27nuu47/u%2B4HPtB2HocR37kch1Hscx/HXvh3HifRynycB2nCcZ9nNsM8QmBs%2BZxkKUCbrMocJIcsyHDTLQnBArwXjcLwqCcD4PgAGoALKrAAkgAStyszzJgsK1rwBCaDX0wANYgJIbqMySpmSKcNwkm6y/nKcHp1xwkiN1PpCtxwvAKCAoKTxwWjTHAsBIGgXN0OE5CUI/MTPxEeDzAYRgEMQWIZ58DoAQcI58IAhCPhJZgDJOA8FINAqo9IADyIRtDCjgbwR%2BgECDIIYLQRk19eBYBCG4YATgxC0HPs3UgWAWCGGAOIIhtDv7CjwEKahWhSCYFUKUNwoDMHkEEE0I%2BtA8AhGIEglwWAj7/zwCwQRQpiAhHiJgDkAEGFiKMFPaYAomDAAUB3PAmAADuyCYiMEEfwQQIgxDsCkDIQQigVDqGYboBov9jBmAsGIkI59IDTFQDEFo1DtrIPZNteh8wEADWFgwJRkQW5KOIHgLA/iIDTBKGUewEBHCDHqKCXw/guj5B6GvWI8REgCHyRIUEGQqkMDGN0CI5SsktDaAMVwdRamNGaOUfoHRinjDKa6EYnTUgFMsAMpppSWk3EycPBYUx9D10Pswk%2BqxkCeNWBAf%2BgDUQQFwIQAy2YuCTAnjo2eIAQSM0%2BBOXce0NB3PbGtPeB9SAKK9KCJuXCT5nwvqQK%2BN9a6cE%2BGs35nALlEMmNMJRCR7CSCAA%3D%3D)
[Zig Godbolt](https://zig.godbolt.org/#g:!((g:!((g:!((h:codeEditor,i:(filename:'1',fontScale:13,fontUsePx:'0',j:3,lang:zig,selection:(endColumn:1,endLineNumber:12,positionColumn:1,positionLineNumber:12,selectionStartColumn:1,selectionStartLineNumber:12,startColumn:1,startLineNumber:12),source:'const+std+%3D+@import(%22std%22)%3B%0A%0Afn+unmovemask64(x:+u64)+@Vector(64,+bool)+%7B%0A++++const+bit_positions+%3D+comptime+std.simd.repeat(64,+@as(@Vector(8,+u8),+@splat(1))+%3C%3C+std.simd.iota(u3,+8))%3B%0A++++return+bit_positions+%3D%3D+(bit_positions+%26+@shuffle(u8,+@as(@Vector(64,+u8),+@bitCast(@as(@Vector(8,+u64),+@splat(x)))),+undefined,+(std.simd.iota(u8,+64)+%3E%3E+@splat(4)+%3C%3C+@splat(4))+%2B+(std.simd.iota(u8,+64)+%3E%3E+@splat(3))))%3B%0A%7D%0A%0Aexport+fn+bar(kinds_1:+@Vector(32,+u8),+kinds_2:+@Vector(32,+u8),+comment_starts:+u64)+@Vector(64,+u8)+%7B%0A++++const+kinds+%3D+std.simd.join(kinds_1,+kinds_2)%3B+//+helps+the+C+ABI%0A++++return+@select(u8,+unmovemask64(comment_starts),+@as(@Vector(64,+u8),+@splat(20)),+kinds)%3B%0A%7D%0A'),l:'5',n:'1',o:'Zig+source+%233',t:'0')),header:(),k:54.37591923954271,l:'4',m:100,n:'0',o:'',s:0,t:'0'),(g:!((g:!((h:compiler,i:(compiler:ztrunk,filters:(b:'0',binary:'1',binaryObject:'1',commentOnly:'0',debugCalls:'1',demangle:'0',directives:'0',execute:'1',intel:'0',libraryCode:'0',trim:'1',verboseDemangling:'0'),flagsViewOpen:'1',fontScale:14,fontUsePx:'0',j:1,lang:zig,libs:!(),options:'-O+ReleaseFast+-target+x86_64-linux+-mcpu%3Dznver3',overrides:!(),selection:(endColumn:1,endLineNumber:1,positionColumn:1,positionLineNumber:1,selectionStartColumn:1,selectionStartLineNumber:1,startColumn:1,startLineNumber:1),source:3),l:'5',n:'0',o:'+zig+trunk+(Editor+%233)',t:'0')),header:(),k:45.62408076045729,l:'4',m:50,n:'0',o:'',s:0,t:'0'),(g:!((h:ir,i:('-fno-discard-value-names':'0',compilerName:'zig+trunk',demangle-symbols:'0',editorid:3,filter-attributes:'0',filter-comments:'0',filter-debug-info:'0',filter-instruction-metadata:'0',fontScale:14,fontUsePx:'0',j:1,selection:(endColumn:1,endLineNumber:1,positionColumn:1,positionLineNumber:1,selectionStartColumn:1,selectionStartLineNumber:1,startColumn:1,startLineNumber:1),treeid:0,wrap:'1'),l:'5',n:'0',o:'LLVM+IR+Viewer+zig+trunk+(Editor+%233,+Compiler+%231)',t:'0')),header:(),l:'4',m:50,n:'0',o:'',s:0,t:'0')),k:45.62408076045729,l:'3',n:'0',o:'',t:'0')),l:'2',n:'0',o:'',t:'0')),version:4)

Zig version:

```zig
const std = @import("std");

fn unmovemask64(x: u64) @Vector(64, bool) {
    const bit_positions = comptime std.simd.repeat(64, @as(@Vector(8, u8), @splat(1)) << std.simd.iota(u3, 8));
    return bit_positions == (bit_positions & @shuffle(u8, @as(@Vector(64, u8), @bitCast(@as(@Vector(8, u64), @splat(x)))), undefined, (std.simd.iota(u8, 64) >> @splat(4) << @splat(4)) + (std.simd.iota(u8, 64) >> @splat(3))));
}

export fn bar(kinds_1: @Vector(32, u8), kinds_2: @Vector(32, u8), comment_starts: u64) @Vector(64, u8) {
    const kinds = std.simd.join(kinds_1, kinds_2); // helps the C ABI
    return @select(u8, unmovemask64(comment_starts), @as(@Vector(64, u8), @splat(20)), kinds);
}
```

LLVM version:

```llvm
define dso_local <64 x i8> @bar(<32 x i8> %0, <32 x i8> %1, i64 %2) local_unnamed_addr {
Entry:
  %3 = shufflevector <32 x i8> %0, <32 x i8> %1, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
  %4 = insertelement <1 x i64> poison, i64 %2, i64 0
  %5 = shufflevector <1 x i64> %4, <1 x i64> poison, <8 x i32> <i32 0, i32 poison, i32 0, i32 poison, i32 0, i32 poison, i32 0, i32 poison>
  %6 = bitcast <8 x i64> %5 to <64 x i8>
  %7 = shufflevector <64 x i8> %6, <64 x i8> poison, <64 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 18, i32 18, i32 18, i32 18, i32 18, i32 18, i32 18, i32 18, i32 19, i32 19, i32 19, i32 19, i32 19, i32 19, i32 19, i32 19, i32 36, i32 36, i32 36, i32 36, i32 36, i32 36, i32 36, i32 36, i32 37, i32 37, i32 37, i32 37, i32 37, i32 37, i32 37, i32 37, i32 54, i32 54, i32 54, i32 54, i32 54, i32 54, i32 54, i32 54, i32 55, i32 55, i32 55, i32 55, i32 55, i32 55, i32 55, i32 55>
  %8 = and <64 x i8> %7, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 -128>
  %.not = icmp eq <64 x i8> %8, zeroinitializer
  %9 = select <64 x i1> %.not, <64 x i8> %3, <64 x i8> <i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20, i8 20>
  ret <64 x i8> %9
}
```

The Zen 3 assembly is:

```diff
.LCPI0_0:
        .byte   4
        .byte   4
 .byte   4
        .byte   4
        .byte   4
        .byte 4
        .byte   4
        .byte   4
        .byte   5
 .byte   5
        .byte   5
        .byte   5
        .byte   5
 .byte   5
        .byte   5
        .byte   5
        .byte 6
        .byte   6
        .byte   6
        .byte   6
 .byte   6
        .byte   6
        .byte   6
        .byte   6
 .byte   7
        .byte   7
        .byte   7
        .byte 7
        .byte   7
        .byte   7
        .byte   7
 .byte   7
.LCPI0_1:
        .byte   0
        .byte   0
 .byte   0
        .byte   0
        .byte   0
        .byte   0
 .byte   0
        .byte   0
        .byte   1
        .byte 1
        .byte   1
        .byte   1
        .byte   1
 .byte   1
        .byte   1
        .byte   1
        .byte   2
 .byte   2
        .byte   2
        .byte   2
        .byte 2
        .byte   2
        .byte   2
        .byte   2
 .byte   3
        .byte   3
        .byte   3
        .byte   3
 .byte   3
        .byte   3
        .byte   3
        .byte 3
        .zero   32,20
.LCPI0_2:
        .byte   1
        .byte 2
        .byte   4
        .byte   8
        .byte   16
 .byte   32
        .byte   64
        .byte   128
.LCPI0_4:
 .byte   20
bar:
        vmovq   xmm2, rdi
        vpbroadcastq ymm4, qword ptr [rip + .LCPI0_2]
        vpbroadcastb    ymm5, byte ptr [rip + .LCPI0_4]
        vpbroadcastq    ymm2, xmm2
        vpshufb ymm3, ymm2, ymmword ptr [rip + .LCPI0_0]
        vpshufb ymm2, ymm2, ymmword ptr [rip + .LCPI0_1]
        vpand   ymm2, ymm2, ymm4
 vpand   ymm3, ymm3, ymm4
-       vpxor   xmm4, xmm4, xmm4
 vpcmpeqb        ymm3, ymm3, ymm4
        vpcmpeqb        ymm2, ymm2, ymm4
        vpblendvb       ymm0, ymm0, ymm5, ymm2 ; deletion of the `vpxor` instruction requires that
        vpblendvb       ymm1, ymm1, ymm5, ymm3 ; the 2nd and 3rd arguments should be switched
 ret
```
</pre>
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-QdE0LRwo5fwNdvfkX9QqPiY95-R_93qPwiVHrP9DfkHRJzJN99LB2afOjDzNfmbbP8fQtlH5IfEJ7x_JP-71TdkcCMUfM32HfIPiLjXi3vM9s_IPyj0lphVKhlvVvsA5sq7wVPvfng2TwzzJGXKTyTfJgLuiVjxidysYrvcBH_eRHVU5TYtM7rb4c4Pd1uapve-n1eDkYNvGDZWFJpO1mVv6YPv56XiNg0jh96QiKYEJcKb_IFwZUVBeyrCyr4ffD9vZnL1HgvhvxKyLYXkCueK33Bmnb2VceRV5Inz4PtfqM08QKzkgO_LYR_IyXoz-pGc05lesJxU5q5ZXiph-zAqzosvt3_-exJm-xu0tU74z4WeNbxb8UzT82l4KHB21nkFU3Ke_gonCTTFKbSDPERwGNDhIn8GTolMvhVKZOiLN650hLYJjlBMk6VJ_ojJlhjsDSaXY2Y4IHDy1piLHNqM3CR_KUzHyzDxHNpCdJxiYi-RU0JFiNwUcb-cN86pcTXzF3pjJSDJMs8xwq_lG5I4UWJqgi1IEnI4juWRg-yFbPNIsGTL-YXfAAN4lmEAKwgsL7w6PMsvasBZAMdhbYajeAb5JvZe81_GhJH7K__hzRvLMrIk_PJMC3lx_pMfAAKU0vksBbIA-xW95b_ZsRI3pnjGwzGJz2IIJl7-WyE4nmbcdPGMCx-RkxnevHh1ZeavqywK1LKTKO2S9XwXtskfpYkMQ1OAfbgsXaKAxoR2QhQHFJBI_rLjVxJ5b__ut0eS8Gv3Bv4vAAD__5l2KR8">