<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/110832>110832</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISC-V] RISCVVectorPeephole::ensureDominates: Assertion `MO.getParent()->getParent() == Src.getParent()' failed.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          hvdijk
      </td>
    </tr>
</table>

<pre>
    Reduced from a real test that is too large to include here.

Please consider `test.mir`:
```llvm-mir
name: f
body: |
  bb.0:
    %0:gpr = IMPLICIT_DEF
    %1:vr = IMPLICIT_DEF
    %2:gpr = IMPLICIT_DEF
    $v0 = COPY %1
 %3:vrm4nov0 = PseudoVLSE32_V_M4_MASK $noreg, killed %0, %2, $v0, 16, 5 /* e32 */, 1 /* ta, mu */
  bb.1:
    %4:vrm4 = IMPLICIT_DEF
    $v0 = COPY %1
    %5:vrm4nov0 = PseudoVMERGE_VVM_M4 $noreg, killed %4, killed %3, $v0, 16, 5 /* e32 */
```
This is not handled by RISCVVectorPeephole:
```
$ llc -mtriple=riscv64-linux-gnu -mattr=+v -run-pass=riscv-vector-peephole -o /dev/null test.mir
llc: /home/harald/llvm-project/main/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp:548: bool {anonymous}::RISCVVectorPeephole::ensureDominates(const llvm::MachineOperand&, llvm::MachineInstr&) const: Assertion `MO.getParent()->getParent() == Src.getParent()' failed.
PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump:
0.      Program arguments: bin/llc -mtriple=riscv64-linux-gnu -mattr=+v -run-pass=riscv-vector-peephole -o /dev/null test.mir
1.      Running pass 'Function Pass Manager' on module 'test.mir'.
2.      Running pass 'RISC-V Vector Peephole Optimization' on function '@f'
 #0 0x0000b4a971a947a8 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (bin/llc+0x3cd47a8)
 #1 0x0000b4a971a91dbc SignalHandler(int) Signals.cpp:0:0
 #2 0x0000e5de7cf3d8f8 (linux-vdso.so.1+0x8f8)
 #3 0x0000e5de7ca17628 (/lib/aarch64-linux-gnu/libc.so.6+0x87628)
 #4 0x0000e5de7c9ccb3c raise (/lib/aarch64-linux-gnu/libc.so.6+0x3cb3c)
 #5 0x0000e5de7c9b7e00 abort (/lib/aarch64-linux-gnu/libc.so.6+0x27e00)
 #6 0x0000e5de7c9c5cbc (/lib/aarch64-linux-gnu/libc.so.6+0x35cbc)
 #7 0x0000e5de7c9c5d2c (/lib/aarch64-linux-gnu/libc.so.6+0x35d2c)
 #8 0x0000b4a96faed9dc (anonymous namespace)::RISCVVectorPeephole::ensureDominates(llvm::MachineOperand const&, llvm::MachineInstr&) const (.isra.0) RISCVVectorPeephole.cpp:0:0
 #9 0x0000b4a96faeddcc (anonymous namespace)::RISCVVectorPeephole::convertSameMaskVMergeToVMv(llvm::MachineInstr&) RISCVVectorPeephole.cpp:0:0
#10 0x0000b4a96faeed2c (anonymous namespace)::RISCVVectorPeephole::runOnMachineFunction(llvm::MachineFunction&) RISCVVectorPeephole.cpp:0:0
#11 0x0000b4a970a588fc llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (.part.0) MachineFunctionPass.cpp:0:0
#12 0x0000b4a9710609e0 llvm::FPPassManager::runOnFunction(llvm::Function&) (bin/llc+0x32a09e0)
#13 0x0000b4a971060c5c llvm::FPPassManager::runOnModule(llvm::Module&) (bin/llc+0x32a0c5c)
#14 0x0000b4a97106178c llvm::legacy::PassManagerImpl::run(llvm::Module&) (bin/llc+0x32a178c)
#15 0x0000b4a96e91e89c compileModule(char**, llvm::LLVMContext&) llc.cpp:0:0
#16 0x0000b4a96e8356fc main (bin/llc+0xa756fc)
#17 0x0000e5de7c9b84c4 (/lib/aarch64-linux-gnu/libc.so.6+0x284c4)
#18 0x0000e5de7c9b8598 __libc_start_main (/lib/aarch64-linux-gnu/libc.so.6+0x28598)
#19 0x0000b4a96e916c70 _start (bin/llc+0xb56c70)
Aborted
```
The assert is in the `RISCVVectorPeephole::ensureDominates` function which documents
```
/// If the register in \p MO doesn't dominate \p Src, try to move \p Src so it
/// does. Returns false if doesn't dominate and we can't move. \p MO must be in
/// the same basic block as \Src.
```
However, when this function is called, no logic is in place that would ensure that `MO` is in the same basic block as `Src`.

Is it the responsibility of previous passes to ensure that the `PseudoVLSE32_V_M4_MASK` is in the same basic block as the `PseudoVMERGE_VVM_M4`, or is it the responsibility of this pass to handle them being in different blocks?
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy8WFtP67zS_jXmZtQqdc4Xvegq9HvRtyqqBULaV5XjOK1fEjuynbLYv35rnLSQUvTSJe0tASE-PPPMweOZMGvlTgkxJ_EPEt_esM7ttZnvD6X8--Wm0OXb_JcoOy5KqIxugIERrAYnrAO3Zw6kBac11MzsBDgNUvG6KwXshRFTEtySYNH_3dSCWQFcKytLYYAkAaJMG2lIEpBwWIb_-5-6PjQTnPTDijWChAuo-lckhq8kXfYDAEUxfUcBACA0xoFda4CEt3C_3vy8X94_bW_vVqNFMxIuDv-whn4DKDoEfn75sPlXj9tPEhqHXkQTKT2s2VjRlfr55-NdSLfP23W0XS8e_x9BlDZiR-gSXmRdi7LXgi57Ev4ZHfzALMG_MRC6InQBIqRA6MK_LWF2HHYMX5vuOPdurNm5saKB5B8p2UPEX-i5vvv1f3fb5-f1dh19oWQ0fg2_qes4ZvrXp720GJdKO9gzVSJk8Qa_7h-Xz8-CO202QrR7XYvPUTe80gjqmsOkcUa2uO7WSMsPSTSppep-T3aqg0nDnDMkvCX0xwEmplOTlll7XDs5eFGTdpAFE438S3EgdKW6uj9E01OE1zX3EU1Xe90IfDDD6pLQlT8JrdF_C-4IXTVMqmEUH7IgdPWExw8nvZLH51jZKW9bEi7iKEM5hdY1kPQHU1q9NbqzJL1Fc4SLL-wULoSynRG3upGKOWEJzfAwO_BM_Io143upxEMrDFMlod5tn6bvlXXGT-Y-HTjks7BWGCe1wsSwfpjuhNswI5QjNCM0n5Dw7mwIAwxj7NHw89WEplAxWYtySEGbn3eLxzuwXdFIBwyKbgdGtNo4zFl751qLFDG8Vjvp9l0x5br5YOWxC6S1HRpgBUyVp5Tn9gK4YXYPBeMvzjB-zICPjvEXKLumPUVcMCVBvjF6Z1gDzOy6RihnvWcG9_5vw2-GfH51Skm1AwQCQtNVp7j3yQYH1kyxnTBoXK2g0WVXC1x1AqLpoC-9BIZxNXmGPrLgGFrw0DrZyH8zlDNAV0exhKYkCip8HHNpGEDwOwiCoIhYns5YHqUs-xBj9s32_2yMVM4b_gk9QWj2vsiw1622zgjWDEEqMXRyIDQ7mZ_QH8HvkJcoAGPqxGB2xmBWFhwe5U6x-i-fbgyh2QDYD9vh7AX-9wREByARlyLlVVhmVYYUeicfSqunVk9nnkhWjUmEo71slibU7z2lBMYM33-MmH6GI2TSQ-KeEWg0As05L0IOhkkrroQOcecIOh5DF6kIAmAFnsDroCnuHEEnZ6xjXvBr-eKeEWh6DlrS60FLOgbNPkROUjFR5qUHPSVhwDrHtj5e86vT8VeJeMiy303HyGgqrWFTtPOle_NyOOfn2pX8z7XjWh2EcY-sEWtmX57XwuzEk35eHy4p-lGHb_HFYxyc8RWDi_-Ir-nUgxrYHNPmJabvc9eRHSWdgMVZVvHPvjyib_xNcOJ1kdAZE3R6y4zrnX4B7zIvOkqGQRLkIvjAa7XBrceb42pGZ8mYMoQ_HSmUH57L5zH_hvy1v73GDhqGvpbNYz6SHZ3JnqXZR9m12DH-NtxG7yzum7Y-MbmOAQoYMYg_hrDIZyLLOXDdtLIWJxX5nhlfLi_G5__nz-f1UisnfrtBZl3zy15ORnKyME4qDliIfqbJUpwcsTzLpUUW8ejarI97RqDZOWicZ7Dd4ratdcy47ZHfVWLiPBuJyc8snPA0gF7AZ92LGKdP-xd4vYnyiyZFAPM1L7YqUvnqkSTBt9N9ErzXSa97yfdQaj5UkZd7mlX_A_eVF2bETlonDAon8bKF9QOUWliswhyUg6B-6tFwjB1n3rBebvThfRysBunOZSDQFH4J1xlloWK1FSCrS_h4P70K4KwfR-zpiU_TWQeFAKnOBaAGljUCCmYlh6LW_AWYxZ3YEFw0wV_6VRywOlvC616gyaV9N6K0wBn2nzivNNR6J_ngnLZmXPQfPF51V5fQe6Mf8Q0L-uPdkReZJQGaMQlGn0XuLUg3-MO2WllZyFq6N9AVtEYcJN5DWEILi6b_KHeImMvfEv6Zz3j7xxYdDUaXoI1H-Iqdt54v7rGF8oUvrmygEFj2SwWlrCqBXVkv1JJwdVPOwzIPc3Yj5rOUplkaZEl6s5-zWTzjSca5ECwqaZGkBQ2qnJUsL7IgjG_knAY0mgUBndEgjZJpWs1EHCZpVfGARwUnUSAaJuspZripNrsb36bNZ7MgC-lNzQpRW_-di1IlXsHPEkpJfHtj5r7DK7qdJVFQS-vsO4yTrvYfyPoOhsS3X31L-HxK_4ud7U1n6vmft66DWQ5z-p8AAAD__139_-4">