<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/109108>109108</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[Aarch64] Recognize simple `Addp` pattern
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
Validark
</td>
</tr>
</table>
<pre>
In Zig:
```zig
const std = @import("std");
export fn addp_attempt(x: @Vector(16, u8)) @Vector(8, u8) {
const a, const b = std.simd.deinterlace(2, x);
return a + b;
}
```
In LLVM:
```llvm
; ModuleID = 'BitcodeBuffer'
source_filename = "llvm_code"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-musl"
; Function Attrs: mustprogress nofree norecurse nosanitize_coverage nosync nounwind skipprofile willreturn memory(none) uwtable
define dso_local <8 x i8> @addp_attempt(<16 x i8> %0) local_unnamed_addr #0 {
%2 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%3 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%4 = add nuw <8 x i8> %2, %3
ret <8 x i8> %4
}
```
In assembly for the Apple M3:
```asm
addp_attempt: // @addp_attempt
xtn v1.8b, v0.8h
uzp2 v0.16b, v0.16b, v0.16b
add v0.8b, v1.8b, v0.8b
ret
```
I think it should just be:
```asm
addp_attempt:
addp v0.16b, v0.16b, v0.16b
ret
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy0VUuPozgQ_jXOxUqEbSBw4JB0JlJL05ddqQ97iQwuEk8bG_mRpPvXrwwhj-7t1c5hUQJF-aviq4fL3Dm51wAVytYo28x48Adjq1eupOD2bVYb8V49a_yX3CO2QskGJdM9T8bfh9yPmsZo57HzAiO2wShNZNcb6xEtEKXOC0QpoiVi63s3cI4Y3GrMheh33Hvo-mhzRmwVnbxC441FtCA5ok84FNEHLR-WiusKRsuLe4wxHhnxuDqK9UDNebFwshMLAVJ7sIo3gGhBI-58TxFb8MFqzDGia1zfqC83n5JwH9Kzxj9_vr58ly-ljt1Fxdb4xYig4Hkz5owu19I3RsA6tC1YRJcj0plgG9i1UoHmHVzANLraRXhM7QD03O7BY8E9V_zdBD9BYd4htoK5LBBbxT-jc0lyxFbDLb7lKWKrPJ1LQiOA0GKuGR11f5Khig8f8Vb26sqFc9sc8nQe9Js2Jz1XUofzvAtOXe1uUW-Dbrw0Gq-8ty5WugvO99bsLTiHtWktANbGQhOsi5LjWnr5AbvGHMHy_aB71w3WJuiT1AK7N9n31sQc4ZNU6lK7Djpj3xEttNEQOyScPK8VjGQEtFIDFs7slGm4wog9FfiMY5p-xB771JWIPZH8tk6zJLocTHdBx9qIHRfCYkRZct-MiGZ0bL5DaFsFx6F38T_5e_qk7Y10Rl_0A7lYlR_xTTKKB4so0ElIJyGfhGISyBVNrnCSIvbjjif7f3iS6XtsErJJWE5CeeV0RZMrnGSPPNOBJxcC63D6VDiaDeHFaCYLC_4LKP2P-5k7B12t3nFrLPYHwKs-tv4L-26Tc3fZ4w_9w4ap9M2F6BbR7Zeeuw6zeJ29Hp5HsijqGOAxWRSHR0z46OmASRYkn0CP0gM-JvCCv_i8d17fJuG_pQj7g9RvWHrsDiYogX-FOG7hd_PzhVr_O6F8JTkTFRMlK_kMKrKkeZ6RdFnMDlWSlDWNGr4sWVbXBBqRC5KXDUnyJC1msqIJTZOSFElJU1YsGkLaFgrGgRVtRjlKE-i4VIs4hRfG7mfSuQAVSUqSFDPFa1BuOFcp1XDCw2qchdlmZqtoNK_D3qE0UdJ5d3PjpVfDgbwaRyrKNvgPaMxeyw_ATnbD1M2TlRA9yhPcx_RZPQtWVQfv-zhPx2baS38I9aIxHaLb4dwZH_Peml_QeES3AyuH6PZC-1jRvwMAAP__Jr80-w">