<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/107289>107289</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Shift by a multiple of 8 on a `i128` could turn into a vector shift
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Validark
      </td>
    </tr>
</table>

<pre>
    https://zig.godbolt.org/z/cjGMW4W64

```zig
export fn foo(v: @Vector(16, u8)) @TypeOf(v) {
    return @bitCast(@as(u128, @bitCast(v)) << 8);
}
```

Znver4:

```asm
foo:
 vpextrq rax, xmm0, 1
        vmovq   rcx, xmm0
        mov     rdx, rcx
        shr     rdx, 56
        shl     rax, 8
        shl rcx, 8
        or      rax, rdx
        vmovq   xmm1, rcx
 vmovq   xmm0, rax
        vpunpcklqdq     xmm0, xmm1, xmm0
 ret
```

Apple-m3:

```asm
foo:
        mov     x8, v0.d[1]
        fmov    x9, d0
        extr    x8, x8, x9, #56
 lsl     x9, x9, #8
        fmov    d0, x9
        mov     v0.d[1], x8
        ret
```

Optimized LLVM:

```llvm
define dso_local <16 x i8> @foo(<16 x i8> %0) local_unnamed_addr {
Entry:
  %1 = bitcast <16 x i8> %0 to i128
  %2 = shl i128 %1, 8
  %3 = bitcast i128 %2 to <16 x i8>
  ret <16 x i8> %3
}

declare void @llvm.dbg.value(metadata, metadata, metadata) #1
```


<details>

  <summary>Unoptimized LLVM dump</summary>

via `zig build-obj ./src/llvm_code.zig -O ReleaseFast -target aarch64-linux -mcpu apple_latest --verbose-llvm-ir -fstrip >llvm_code.ll 2>&1`
```llvm
; ModuleID = 'llvm_code'
source_filename = "llvm_code"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-musl"

%Target.Cpu.Feature.Set = type { [5 x i64] }
%Target.Cpu.Model = type { { ptr, i64 }, { ptr, i64 }, %Target.Cpu.Feature.Set }
%Target.Cpu = type { ptr, %Target.Cpu.Feature.Set, i6, [7 x i8] }

@builtin.zig_backend = internal unnamed_addr constant i64 2, align 8
@Target.Cpu.Feature.Set.empty = internal unnamed_addr constant %Target.Cpu.Feature.Set zeroinitializer, align 8
@Target.aarch64.cpu.apple_latest = internal unnamed_addr constant %Target.Cpu.Model { { ptr, i64 } { ptr getelementptr inbounds (i8, ptr @__anon_227, i64 0), i64 12 }, { ptr, i64 } { ptr getelementptr inbounds (i8, ptr @__anon_230, i64 0), i64 12 }, %Target.Cpu.Feature.Set { [5 x i64] [i64 158329674598400, i64 2251799830972420, i64 1125900041060352, i64 12885032960, i64 0] } }, align 8
@__anon_227 = internal unnamed_addr constant [13 x i8] c"apple_latest\00", align 1
@__anon_230 = internal unnamed_addr constant [13 x i8] c"apple-latest\00", align 1
@builtin.cpu = internal unnamed_addr constant %Target.Cpu { ptr getelementptr inbounds (i8, ptr @Target.aarch64.cpu.apple_latest, i64 0), %Target.Cpu.Feature.Set { [5 x i64] [i64 -6882457295353816576, i64 3831332528523300484, i64 4612917471702155264, i64 47783866528, i64 0] }, i6 6, [7 x i8] undef }, align 8
@start.simplified_logic = internal unnamed_addr constant i1 false, align 1
@builtin.output_mode = internal unnamed_addr constant i2 -2, align 1

; Function Attrs: nounwind uwtable nosanitize_coverage skipprofile
define dso_local <16 x i8> @foo(<16 x i8> %0) #0 {
1:
 %2 = bitcast <16 x i8> %0 to i128
  %3 = zext i7 8 to i128
  %4 = shl i128 %2, %3
  %5 = bitcast i128 %4 to <16 x i8>
  ret <16 x i8> %5
}

attributes #0 = { nounwind uwtable nosanitize_coverage skipprofile "frame-pointer"="none" "target-cpu"="apple-latest" "target-features"="-a510,-a520,-a65,-a710,-a720,-a76,-a78,-a78c,-addr-lsl-fast,+aes,-aggressive-fma,+alternate-sextload-cvt-f32-pattern,+altnzcv,-alu-lsl-fast,+am,+amvs,+arith-bcc-fusion,+arith-cbz-fusion,-ascend-store-address,-b16b16,-balance-fp-ops,+bf16,-brbe,+bti,-call-saved-x10,-call-saved-x11,-call-saved-x12,-call-saved-x13,-call-saved-x14,-call-saved-x15,-call-saved-x18,-call-saved-x8,-call-saved-x9,+ccdp,+ccidx,+ccpp,-chk,-clrbhb,-cmp-bcc-fusion,+complxnum,+CONTEXTIDREL2,-cortex-r82,-cpa,+crc,+crypto,-cssc,-d128,+disable-latency-sched-heuristic,-disable-ldp,-disable-stp,+dit,+dotprod,+ecv,+el2vmsa,+el3,-enable-select-opt,-ete,-exynos-cheap-as-move,-f32mm,-f64mm,-faminmax,+fgt,-fix-cortex-a53-835769,+flagm,-fmv,-force-32bit-jump-tables,+fp16fml,-fp8,-fp8dot2,-fp8dot4,-fp8fma,+fp-armv8,-fpmr,+fptoint,+fullfp16,+fuse-address,-fuse-addsub-2reg-const1,-fuse-adrp-add,+fuse-aes,+fuse-arith-logic,+fuse-crypto-eor,+fuse-csel,+fuse-literals,-gcs,-harden-sls-blr,-harden-sls-nocomdat,-harden-sls-retbr,-hbc,+hcx,+i8mm,-ite,+jsconv,-ldp-aligned-only,+lor,-ls64,+lse,-lse128,+lse2,-lut,-mec,-mops,+mpam,-mte,+neon,-nmi,-no-bti-at-return-twice,-no-neg-immediates,-no-sve-fp-ld1r,-no-zcz-fp,+nv,-outline-atomics,+pan,+pan-rwv,+pauth,-pauth-lr,+perfmon,-predictable-select-expensive,+predres,-prfm-slc-target,-rand,+ras,-rasv2,+rcpc,-rcpc3,+rcpc-immo,+rdm,-reserve-x1,-reserve-x10,-reserve-x11,-reserve-x12,-reserve-x13,-reserve-x14,-reserve-x15,-reserve-x18,-reserve-x2,-reserve-x20,-reserve-x21,-reserve-x22,-reserve-x23,-reserve-x24,-reserve-x25,-reserve-x26,-reserve-x27,-reserve-x28,-reserve-x3,-reserve-x30,-reserve-x4,-reserve-x5,-reserve-x6,-reserve-x7,-reserve-x9,-rme,+sb,+sel2,+sha2,+sha3,-slow-misaligned-128store,-slow-paired-128,-slow-strqro-store,-sm4,-sme,-sme2,-sme2p1,-sme-f16f16,-sme-f64f64,-sme-f8f16,-sme-f8f32,-sme-fa64,-sme-i16i64,-sme-lutv2,-spe,-spe-eef,-specres2,+specrestrict,+ssbs,-ssve-fp8dot2,-ssve-fp8dot4,-ssve-fp8fma,+store-pair-suppress,-stp-aligned-only,-strict-align,-sve,-sve2,-sve2-aes,-sve2-bitperm,-sve2-sha3,-sve2-sm4,-sve2p1,-tagged-globals,-the,+tlb-rmi,-tlbiw,-tme,-tpidr-el1,-tpidr-el2,-tpidr-el3,-tpidrro-el0,+tracev8.4,-trbe,+uaops,-use-experimental-zeroing-pseudos,-use-postra-scheduler,-use-reciprocal-square-root,-use-scalar-inc-vl,+v8.1a,+v8.2a,+v8.3a,+v8.4a,+v8.5a,+v8.6a,-v8.7a,-v8.8a,-v8.9a,+v8a,-v8r,-v9.1a,-v9.2a,-v9.3a,-v9.4a,-v9.5a,-v9a,+vh,-wfxt,-xs,+zcm,+zcz,-zcz-fp-workaround,+zcz-gp" }

!llvm.module.flags = !{}
```

</details>
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJysGV1v3Dby18gvAhcS9bHaBz_4Iz4UaC5Am2sP92JQ1GiXCUUyJCWv_esP_JB2tXbSuHdFs5wvzgxnhkOKJsawvQC4TqrbpLq_IqM9SH39B-GsI_rrVSu75-uDtcokxU2CHxL88ML2m73sWsntRuq9oyT4gX75x8c_yz_rMsnuk-wm_tZZ-P-F7QMFjkpqm_Yi7aVMcDMlxU2alNkfQK3UCW7yOsF36dgkeJfgnWN9flbwqfeyjrC9DZrSNE012FELJ9Qye0eMTXCTlBkxCW7GHDdO1Yo5zWqLu6S4S72VIipMtvcXXp8v5T9iAl26ILy1PmKGQHGrmmXSScHR6m-pJkfnyXEYMjfmpwW4_6ZBTt_cYuhJaiUwyMmPuvMCTm7FNwd9zq_qSzYP7OBF85obLV9wZNA6z3Pa3_T7OAz52q8zjl-w07Ceqkah6Ff-rfvm8VlwVnUWAw32B1m5UYoDGor35eUirkdfJ1O26ZLqNk-q-7VYH-WOOyfWXSTHZfikJP56yQQXSyq4CTkInIXfvG2py6LUm-6eOxpMrsR-HLBPyrKBvUCX_vrrHx-_FzbOpxi3DnomIO2MfOSSEu52Tl6nx5Q1SfHBba6wjy_IuMrcNvNTHkchyADdI-k6fdq_H4TVz2c5SXCVp0lxn7bMUmLspSVcZamVKXPb-jQF-ymuiB3DK1mVcoKrYqV1FsNO2crEPEXDG7aLyx4Ro0M50ZBOknUuFi5um67dbybCR0hwM4AlHbHE-fQ2vHN1kP8gY_G3uOvAEsbN4umyxOLOjMNAXDQ__EvIVYbTbhyU63b44SR0Pn9iJA0NOm1Hxjsk2y_pxolrmuAHt6JHKjvYOAn0Kf0NOBADDy6WyBK9B5sSoumhLhFnYjymaKBqTInbmY-cWHCCaALdSgPI6UNMp6g3VjOVJsWHkwnOU-zcw3V-CsLrmkyK2_Sj7EYOv9z73CZ4uyhJ8DZIGTlqCo894-DKLwriM0EcBOMiXDo4eZajnUUBDUlxA8gVwY37V2DE8jopbvyPw2p3ItQl8lVZ3OS4QaLAgfa7P4DWRtya-eLLHLdRfBXySYT4oWE0fJkXf3H12SvY3Klx8wDEjho2v0Nw1T4rcPsqTarbyhVtXSbVfXqq1dXsj7IDfjFve5sqq11hsrr0E11_epv6fVfetLe2FPV9V0kw5kWq223YgKulhN8yc7VqmXBV-dgS-hVE5y0xYUELwtNV06FSGEuE9QvBTj3hbC_mNuEuGW-6s4FB2eefUfz9sLyAlkwwywhnL6B_YDyWw4aqcbPaPu-2H3P8ZmpnUroHCxwGENZhTLRyFJ1JE9wwf4o5alJmj49ESPGI8XZWkvlLVIBz_P1y-buWiuwvLP2gBF9tgurWT66aAu_qbVntmjJb9GNc5dvdrimy3RaXeKHnOa52WZaVeVZnRYVPPjRNlTlNZy6G-pydu8ztKXw_lcbqNi-WsqeuR5wVQlLdOd_PCjh_ZafI_gc76K_tzBuPxq39nrp8b0H8xb64rJK_UReobhpcVlu8q4qqaPK62taz2qIp8qLAFW4qXBRZVjblzCrrHO_ybbnNtxnOqwrXJ9Z22xRNXVfh6-O8RAKevm5vo-ig_14BGUu03Rg2KM56Bt0jl3tGf6rZ5WlPuIEfpVGOVo32cZAd_JRKnKI3ymI5lh9GQS2TIr2xVrtPxlTIUTwx0aXjkyUth1RIQ1w7fIFHKifQZA-p-cqU0tKd1f-Pa2fid8F80cxPl8zlwviuO2a4QL7A0aZsmzZvSJSvbqE4FmRxJlW9eREt33cRrd68iBJrNWtHCyYuvgjd973Rd7eSXpMBkJK-FFwXKO4TjIUU7srkBMJdBlE1LtxV91hJ9WEbmkUUkSp33RORCoexrvywjeRtJPudiMi2iQP1Y9dpxA1Hvf-gv0vwLXHK7xDZ7zUYwyZA_UAii_tqtoAMHC2XpEN0sqgvMFLEOt4iJ17o5NXw8VL_MI-TiZBm9oBaSlE_GibFOZW2LycqIoaC6JCxUoP3HYx3ts3r1r90oJZwIiigXiGpov62jzzdQqRY5giUcI4MmaBDxxCtFSV_RcGvKMUrSvmKUr2iNJeUV4RdcJTSTs0Q8-8RHlTKyx---oHr9tB6aFCvwkjloPhRjDHqd5_--fnDvz__cv_bh1_DaqS2cES6CZiKqabucyUAz8pKzzPG10wXXoISfNsx43aBL1RBn5GhB-jQAUbNjGVBeBbx61hQY9WsIpZFJ63SsgsI-OJxAMfTYMiM-GiDCCqAA7VIKuuJFvxwfBbSIHoAohAxaJCTp_cFHgYP1GUEyMDEQGJI-73X0rPjHBBSFagpqm0dM9Fzsg8TB1_YvdQUUIFbZtGXcVDIN4RYcb3K637gXk41ceikxSewjOCyuXqFiB6mKD3omWpd54jIyLlTPWNmtQlm3Iwtwhr2yB8z-RlLK8c_n7047DG_4_x5eEYNBYBA6nOiAX6GcmZBE-7d2FM_HIjuQCDDDWq5vqAISeXQEXtB1mDbINpGDw40Jog1IW3Mxi38xVApfCZ4p5A_P6FDUvDnwOfeX8SNv0s4gj-5ETew1C834DPCR-_JAL5kh6VxDMo3KzTMRgWEPiQG3z-ERK1liFgUXk6RfWIUIkfAHrFhgI65Nh6JZvKtiXe5jpQX-oL6uBnCeuRoOROAiJUDo9EVRcQCIP00zchoD26OBxCPKVKg-yF4qjR0jNrzHQNHBcI19iisodPBQaX7ARlO40OEI2kiYsFoYgLBTDhSqPIBc2NxIrlVy4h2Pn4aDOgJ0DFfY9kaveDiNVqs0XKNVmu0WaFrTXhtFq_N4gvhtVm8NovXZnG9RrdrdO3UWnGxdmptZm1lbWRtY-exIabWtHEEHlNmDuQEeQ8Ml09oYGbeQTlu_PG68BRhOtAXkrH6m5boJDeUYYhY2FVuVHmEUJ_X8Rj2WF32dblgzTmr6Qu8IOQkxfKanTA-2imIKYgDAugjSDWYeaEBs5rR2EaNaX0pm7Abl8Z8hpfn-NKiw73DBQSZUam58Rr7qgGhYC-QPR7OITPF2EyAY_cNcMusAj0s-JIej8T4TnNALdnvoUN7LtvYde0h5tzyFunQnixv2ZMHQmKsYp1GwPNzBJ8jxYJoiYBnUaUmFKZm452wyyVqJKFRIncCuKaimfsEJRyFN5o9UgbGTi4yShqrSbgljNy_3Xi6BsqUdt8lyHwbiQakpbQz11DCiUZMUDTFM2dqNjlZQHwCixNYnsDqBNYORFOz2c5AMwO7RSpSvH_TLphyAJ6BYgbKGagiMOvwTfmpP_pVHGMPf6HDDLw4emj96Enqr0S7T_aFi_bKX_sv3ulw7l_EB_9Yu3E3EhPfPnP3efbDP7iFR-vTo_dVd110u2JHruA63-Kq3NZlkV8drjEhfUXLPKOkz7Jt29a0In3ZbHNMSEerK3aNM1xmu6zMd1lW5Btcka5qs2zX1ru-yJqkzGAgjG-8t1Lvr5gxI1zn2RY3uytOWuDG_4UUYwFPqee6D5rq_kpf-yftdtybpMw4M9ac1FhmOVz_fmC9TdvnlKTDyK1_AZZ92qRSpP7x3X9N1llK5ci71P9JkwkrU5JO_s-iqXEarkbNL_4Uu2f2MLYbKof4VB8HpLT8Aq59PHhfTYIf4mKma_zfAAAA__-V79AN">