<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/107034>107034</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [X86] Non-optimal codegen for bool to float conversions with `select i1 %0, float 1.0, float 0.0`
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          soooch
      </td>
    </tr>
</table>

<pre>
    https://godbolt.org/z/3jjdq1ex1

Given the following Rust source:

```Rust
#[no_mangle]
pub fn ifelse(x: bool) -> f32 {
    if x { 1. } else { 0. }
}
```

We end up with the following before x86 inst selection:

```llvm
define noundef float @ifelse(i1 noundef zeroext %x) unnamed_addr {
start:
  %. = select i1 %x, float 1.000000e+00, float 0.000000e+00
  ret float %.
}

```

For which we end up with the following x86 codegen:

```asm
.LCPI1_0:
        .long 0x3f800000
ifelse:
        test    edi, edi
        jne .LBB1_1
        xorps   xmm0, xmm0
        ret
.LBB1_1:
 movss   xmm0, dword ptr [rip + .LCPI1_0]
        ret
```

Ideally we'd probably like to see this converted to:

```llvm
define noundef float @cast(i1 noundef zeroext %x) unnamed_addr {
start:
  %_0 = uitofp i1 %x to float
  ret float %_0
}
```

On x86, this would give us:

```asm
cast:
        cvtsi2ss        xmm0, edi
 ret
``` 

On the integer side, `InstCombinePass` is able to transform `select i1 %x, i32 1, i32 0` to `zext i1 %x to i32`. That seems like a somewhat similar operation, but I'm not very familiar with LLVM.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJysVVGP4jYQ_jXmZbSR4xAIDzwcS6lW2ranqmr7hpx4Qrx1PKntAHu_vnIS2IW7bauqEcLJeOyZ75vPHum9PljENcs3LN_OZB8acmtPRFUzK0m9rpsQOs-yT0zsmNgdSJVkQkLuwMTuCxO77OVF_ZniOWV8y_in8f97fUQLoUGoyRg6aXuAn3sfwFPvKozbvfNmCz7-ostkEhnLN5b2rbQHgyzfjvauL6G2oGs0Hpkoziz7BCWRYWIFDyz7DupMAFtuRncAAF3DOVogTYAttxBXDt98-J7iXV8uubxP8DcEtAr6Dk46NHe4SqzJIZyLBWgbIaLBKmiyH6E05tiOJoW1tgiWequwhtqQDMDm_ApPp9fJL-gIzwGYyM8RbG-tbFHtpVLuDbAP0oVrYIjeCbBsO2UFOp02eJyipQkfHmRiw_mbnd_ap-0chkuWIk_uqfuYwB05ODW6auD0d1RGDitSeMAPyZN-4i55fvz8lO75O7DjkxiyB-DnrC4GBOPsROm9c0Af4ohKR-xxuJl_sQjJ82aT7tPbiTO5zsexbQfWhvHGw2G4ZDquv8Zu6ejfr1Uncgq64IDlG6c7YGIDV3wX6X-17zeZflIojXmFEzKxVNA5KmVpXsHoPxACgUeE0GgPFdkjuoAKAv13pVbSh_9Jp3s-CLXXgeruItSY8hDsmwrc839zen-yUViR6AH4iXqj4KCPCL3_R5kNAO9VUx2D12Ko4SiGqZBv8vm6SHCXUlS-tgEP6MBrhXE9W_An68MjtaW2-Fl6HxdqD7I0Q_WCk9bX5Nro-vWR1pmA9PIyBA0UPb_EgrxjVGeCLXgCvzQy3lfY-lEfEjy1eBqsutVGOqAOnRxuM_EIZR_giYllC5YCHNG9Qi1bbbR043F-fv71h2Sm1plaZSs5w3W6FHkm8rwoZs16nhbzIpdpWZblqlZpVS3TfImiEKouxKKa6bXgYs5XPOMpX4giKVQ2xzKtVlWO80whm3NspTZJVGZsQjPtfY_rlC95Np8ZWaLxQzMTwuIJhlkmROxtbh0XPZT9wbM5N9oH_7ZN0MEMXfD3YsHyLfxI9oG6oFtpLjcS1OSGVnPV5HSGvCbrR_z3VeE3F-3N7coWfNY7c99fdWj6MqmoZWI3HL9xeOgcvWAVmNgNmDwTuwn0cS3-CgAA__98qjrl">