<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/106700>106700</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV][SiFive] How to prevent reordering of VCIX instructions when using intrinsics and inline-asm?
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          michalt
      </td>
    </tr>
</table>

<pre>
    We've run into an interesting problem when writing some high-performance kernels that use the VCIX instructions.

In a few places we wanted to use both intrinsics and a small amount of inline assembly (it's performance critical and writing it manually was a noticeable win). This turns out to be tricky because the compiler reorders the intrinsics and the inline-asm block. VCIX instructions should not be reordered across each other, and this is accomplished through `VCIX_STATE` ([code](https://github.com/llvm/llvm-project/blob/1b32c3e2985f89900030289eaa44e3d92cab85af/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp#L147-L148), #77049). This works fine when using intrinsics, however, we couldn't find a way to indicate that `VCIX_STATE` gets clobbered by inline-asm.

Is this something that's possible and we just missed it? If not, what would be the best approach here?

@4vtomat @topperc @michaelmaitland Any suggestions would be very welcome! 🙂 

Simplified repro: https://godbolt.org/z/KcT3asrKa


</pre>
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