<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/105814>105814</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[AMDGPU] LiveIntervals appears to track SGPR arguments using lo/hi16
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
Pierre-vh
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
Pierre-vh
</td>
</tr>
</table>
<pre>
I ran some tests on a large application, and I've seen the following (through printf debugging)
```
Very Large LR (859) for SGPR4_LO16
Very Large LR (859) for SGPR4_HI16
Very Large LR (859) for SGPR5_LO16
Very Large LR (859) for SGPR5_HI16
Very Large LR (859) for SGPR8_LO16
Very Large LR (859) for SGPR8_HI16
Very Large LR (859) for SGPR9_LO16
Very Large LR (859) for SGPR9_HI16
Very Large LR (859) for SGPR12_LO16
Very Large LR (859) for SGPR12_HI16
Very Large LR (859) for SGPR13_LO16
Very Large LR (859) for SGPR13_HI16
Very Large LR (859) for SGPR14_LO16
Very Large LR (859) for SGPR14_HI16
```
We have some places were the dispatch ptr, implicit arg ptr and/or x y z coords arguments are tracked using the lo/hi16 registers.
This is because SGPRs appear to have 2 regunits for the lo/hi16, even though the high16 is artificial.
I'm not sure of the impact of this, but RegisterCoalescer appears to take a long time in this application. I think it's just kinda slow overall but I am curious if fixing this would improve performance. We have 859 segments and we have to do the job twice for the lo/hi16, and it's highly likely both RUs are identical.
Should we even have a regunit for the lo16 register? Maybe we could get rid of the sgpr4_hi16 regunit and have sgpr4_lo16 == sgpr4 sharing the same regunit.
I think lo16 SGPRs aren't addressable anyway so this would just be an optimization.
We seem to have a lot of room to optimize our register file. It'd be really nice to not have those lo16/hi16 SGPR registers at all.
cc @arsenm @jayfoad
</pre>
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