<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/101526>101526</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] float to int conversion intrinsics are incorrectly enabled without Zfh.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:RISC-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
            4vtomat
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          topperc
      </td>
    </tr>
</table>

<pre>
    We have this code in SemaRISCV.cpp to disable f16 intrinsics without Zvfh.

```
      if (BaseType == BasicType::Float16) { 
        if ((Record.RequiredExtensions & RVV_REQ_Zvfhmin) == RVV_REQ_Zvfhmin) {  
          if (!TI.hasFeature("zvfhmin"))                                         
 continue; 
        } else if (!TI.hasFeature("zvfh")) { 
          continue; 
        } 
      } 
```

For the conversion intrinsics, the BaseType is integer, not floating point, so we miss this check if any of the source operands are Float16.

CC: @jacquesguan @kito-cheng @rofirrim 
</pre>
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