<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/101155>101155</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[RISCV] Improper instructions were generated for global register variables sepcified by `-ffixed-reg` option.
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
wan-yuqi
</td>
</tr>
</table>
<pre>
Define a callee-saved RISCV register as a Global Register Variable. The prologue/epilogue instructions of the register will be generated, which will cause the value of the global register variable to be unexpected. [GCC Global-Register-Variables](https://gcc.gnu.org/onlinedocs/gcc/Global-Register-Variables.html#Global-Register-Variables)
```C
register void* x18 asm("x18"); // aka s2
void callee_saved() {
x18 = (void*)0x10000;
}
```
compiling with option `-ffixed-x18`
```
callee_saved:
addi sp, sp, -16
sw s2, 12(sp)
lui s2, 16
lw s2, 12(sp)
addi sp, sp, 16
ret
```
The value set for `s2` register by `lui s2 16` will be overwritten by the subsequenct `lw s2` instruction.
compared with GCC:https://godbolt.org/z/WKKxT7sz8
Which I can find the earilest PR regarding the support of the `-ffixed-reg` option for RISCV is [D67185](https://reviews.llvm.org/D67185). Perhaps it was inspired by ARM's support by `-ffixed-reg`([D56005](https://reviews.llvm.org/D56005)).
However, after reviewing the modifications in this PR, I found that it only implements the behavior that the complier will not allocate the specified RISCV register when using the `-ffixed-reg` option, and may report errors in some scenariors. It appears to have ignored the prologue/epilogue instructions generated by compiler for callee-saved register used in function.
I dont know if anyone has already discovered this issue or has any solution.
</pre>
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