<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/101040>101040</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] Missing fold with cascade shifts when compiling with zbb
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:RISC-V,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          dtcxzyw
      </td>
    </tr>
</table>

<pre>
    Reproducer (sampled from pybind11): https://godbolt.org/z/rc95a37ej
```
; bin/llc -mtriple=riscv64 -mattr=+zbb test.ll -o -
define i64 @func0000000000000005(i64 %0, i16 signext %1) #0 {
entry:
  %2 = shl i16 %1, 9
  %sext = ashr i16 %2, 15
  %3 = sext i16 %sext to i64
 %4 = add nsw i64 %3, %0
  ret i64 %4
}
```
With zbb:
```
func0000000000000005:                   # @func0000000000000005
        slli    a1, a1, 9
        slli    a1, a1, 48
        srai    a1, a1, 63
        add     a0, a1, a0
 ret
```
Without zbb:
```
func0000000000000005: # @func0000000000000005
        slli    a1, a1, 57
        srai    a1, a1, 63
        add     a0, a1, a0
 ret
```
```
Optimized legalized selection DAG: %bb.0 'func0000000000000005:entry'
SelectionDAG has 16 nodes:
  t0: ch,glue = EntryToken
              t4: i64,ch = CopyFromReg t0, Register:i64 %1
 t6: i64 = AssertSext t4, ValueType:ch:i16
          t19: i64 = shl t6, Constant:i64<9>
        t20: i64 = sign_extend_inreg t19, ValueType:ch:i16
      t21: i64 = sra t20, Constant:i64<15>
      t2: i64,ch = CopyFromReg t0, Register:i64 %0
    t15: i64 = add nsw t21, t2
  t17: ch,glue = CopyToReg t0, Register:i64 $x10, t15
  t18: ch = RISCVISD::RET_GLUE t17, Register:i64 $x10, t17:1


===== Instruction selection begins: %bb.0 'entry'
```
As we discussed in https://github.com/llvm/llvm-project/pull/100966#issuecomment-2255041313, `sra (sign_extend_inreg X), C` can be folded into `sra + shl` in DAGCombine.

</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy8Vttu4zYQ_Rr6hbDBiy7Wgx8cKV4EaFEgSbd9W1DS2OIuRRoktY7z9QUpub4kWbRboIIRSeGZwzmHM6SEc3KnAVYovUNpNROD74xdtb55eT0eZrVpj6tH2FvTDg1YjNjSiX6voMVba3q8P9ZSt5QiViC-xp33e4f4GrENYpudaWuj_MLYHWKbV8Q2tilSwXP4ikiFyBplZPqNr_wO11IjtlGqwfPeW7lXgHhlpWu-Zwme98J7i3iF2N1rXWMPzi-UwnOD5yNFC1upAcsswSgh20E35PpKEVvGUZYSxEosaYajAy8-_C8IwYhxglF-N1KC9vYYNMU3HFAMI15h16kYPoaVuLhAuMjHKyxcZ08oFlA0vYDxkSiAJ0x89iYomHCIpclI1bZYuwOe0ueBLcqY-Cz409gUi_LqXaP_kL7Dr3X9t6qb8Xd942v89kKMf2j0lNZ4OaVkuItolbg27GNIsrzBWPEGk_FrTPAp3skZI04uWfAfWmIG_zOu_CcP0vx_Enjz-tvey16-QosV7ISKTw4UNF4ajav1p1FZWtcLghHLPxA_NgebRDydCKr1J9wJh2mGtWnBXbSPJ4G56RArd2qAWNn3geXZfAN9LXS8fBIiQkOwsuliQGn2x401_SPsAiEr8SPspPNgEV9PPUAnLp9N4TFy7RxY_xS7LBDiz0IN8HzcA-LrpgvhNLvNwtPikiM0vs9CcGm080L7cVbEywLx--toz8hVrNzpL_DiQbdfpLYhf1r8kzw8o1c8VkTq95Kg6U0Wnv2Ug-TM4Wl6OftpKwpJsTLwn1aX5m-XN8z1bH4wU_JC44A_b46eLkeiyPD48FR-fniqQh3x9eP985dPv_x-H2f7MV_IZiqEq7-8uvzhB-28HcbaP3dBDTup3U0jXFf8TVetHT4AbqVrBuegxVLfHonSd0O9aEwfT7nvp9t8b81XaDxim_2gFGIbSkiRZYhx6dwAjel70H7OWJqShHI67v4ZCXUQDuU3ZfVnOJJDdaCM4EYENXhrVBuz8uYcexfqOYBk7PvS9LXUsBgFzdoVbwteiBmsaM4Yy3meprNulaaQABEsZ0nOc0o54Sltku12CVnBm2ImV4ywhOSsCHE8XWwLAJqTpOBQZ8s6RQmBXki1CPrDN8IsKl1RQklCZkrUoFz8LGGsFs030G1Y-4encv4ZsXCWIsZ6GXyem3E3E2HZwlhazewq-loPO4cSoqTz7jyTl17FT55YWCit8K_SOal30SJ8COdjI1wjWsCuk1vv8KEDjRvT76UKuMN0hM4Gq1b_eo2jUhdXOYr9vmJ_BQAA__9CgJDC">