<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/99163>99163</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
Implement the `WaveActiveBallot` HLSL Function
</td>
</tr>
<tr>
<th>Labels</th>
<td>
metabug,
backend:DirectX,
HLSL,
backend:SPIR-V,
bot:HLSL
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
farzonl
</td>
</tr>
</table>
<pre>
- [ ] Implement `WaveActiveBallot` clang builtin,
- [ ] Link `WaveActiveBallot` clang builtin with `hlsl_intrinsics.h`
- [ ] Add sema checks for `WaveActiveBallot` to `CheckHLSLBuiltinFunctionCall` in `SemaChecking.cpp`
- [ ] Add codegen for `WaveActiveBallot` to `EmitHLSLBuiltinExpr` in `CGBuiltin.cpp`
- [ ] Add codegen tests to `clang/test/CodeGenHLSL/builtins/WaveActiveBallot.hlsl`
- [ ] Add sema tests to `clang/test/SemaHLSL/BuiltIns/WaveActiveBallot-errors.hlsl`
- [ ] Create the `int_dx_WaveActiveBallot` intrinsic in `IntrinsicsDirectX.td`
- [ ] Create the `DXILOpMapping` of `int_dx_WaveActiveBallot` to `116` in `DXIL.td`
- [ ] Create the `WaveActiveBallot.ll` and `WaveActiveBallot_errors.ll` tests in `llvm/test/CodeGen/DirectX/`
- [ ] Create the `int_spv_WaveActiveBallot` intrinsic in `IntrinsicsSPIRV.td`
- [ ] In SPIRVInstructionSelector.cpp create the `WaveActiveBallot` lowering and map it to `int_spv_WaveActiveBallot` in `SPIRVInstructionSelector::selectIntrinsic`.
- [ ] Create SPIR-V backend test case in `llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBallot.ll`
## DirectX
| DXIL Opcode | DXIL OpName | Shader Model | Shader Stages |
| ----------- | ----------- | ------------ | ------------- |
| 116 | WaveActiveBallot | 6.0 | ('library', 'compute', 'amplification', 'mesh', 'pixel', 'vertex', 'hull', 'domain', 'geometry', 'raygeneration', 'intersection', 'anyhit', 'closesthit', 'miss', 'callable', 'node') |
## SPIR-V
# [OpGroupNonUniformBallot](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpGroupNonUniformBallot):
## Description:
Result is a bitfield value combining the *Predicate* value from all
invocations in the [group](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Group) that execute the same dynamic
instance of this instruction. The bit is set to one if the corresponding
invocation is active and the *Predicate* for that invocation evaluated
to true; otherwise, it is set to zero.
*Result Type* must be a vector of four components of [*integer
type*](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Integer) scalar, whose *Width* operand is 32 and whose
*Signedness* operand is 0.
*Result* is a set of bitfields where the first invocation is represented
in the lowest bit of the first vector component and the last (up to the
size of the group) is the higher bit number of the last bitmask needed
to represent all bits of the group invocations.
*Execution* is a [*Scope*](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Scope_-id-) that identifies the group of
invocations affected by this command.
*Predicate* must be a [*Boolean type*](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Boolean).
[Capability](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Capability):
**GroupNonUniformBallot**
[Missing before](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Unified) **version 1.3**.
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</colgroup>
<thead>
<tr>
<th>Word Count</th>
<th>Opcode</th>
<th>Results</th>
<th>Operands</th>
<th></th>
<th></th>
</tr>
</thead>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p>5</p></td>
<td class="tableblock halign-left valign-top"><p>339</p></td>
<td
class="tableblock halign-left valign-top"><p><em><id></em><br />
<em>Result Type</em></p></td>
<td class="tableblock halign-left valign-top"><p><a
href="#ResultId"><em>Result <id></em></a></p></td>
<td class="tableblock halign-left valign-top"><p><a
href="#Scope_-id-"><em>Scope <id></em></a><br />
<em>Execution</em></p></td>
<td
class="tableblock halign-left valign-top"><p><em><id></em><br />
<em>Predicate</em></p></td>
</tr>
</tbody>
</table>
## Test Case(s)
### Example 1
```hlsl
//dxc WaveActiveBallot_test.hlsl -T lib_6_8 -enable-16bit-types -O0
export uint4 fn(bool p1) {
return WaveActiveBallot(p1);
}
```
## HLSL:
Returns a uint4 containing a bitmask of the evaluation of the Boolean expression for all active lanes in the current wave.
## Syntax
``` syntax
uint4 WaveActiveBallot(
bool expr
);
```
## Parameters
<dl> <dt>
*expr*
</dt> <dd>
The boolean expression to evaluate.
</dd> </dl>
## Return value
A uint4 containing a bitmask of the evaluation of the Boolean expression for all active lanes in the current wave. The least-significant bit corresponds to the lane with index zero. The bits corresponding to inactive lanes will be zero. The bits that are greater than or equal to [**WaveGetLaneCount**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/wavegetlanecount.md) will be zero.
## Remarks
Different GPUs have different SIMD processor widths (lane counts). Most of these **WaveXXX** functions are able to operate at level of abstraction where SIMD machine width is concealed. To maximize portability of code across GPUs, use the intrinsics that don’t rely on machine width. For example, use:
``` syntax
uint result = WaveActiveCountBits( bBit );
```
Instead of:
``` syntax
uint result = countbits( WaveActiveBallot( bBit ) );
```
This function is supported from shader model 6.0 in all shader stages.
## Examples
``` syntax
// get a bitwise representation of the number of currently active lanes:
uint4 waveBits = WaveActiveBallot( true ); // convert to bits
```
## See also
<dl> <dt>
[Overview of Shader Model 6](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/hlsl-shader-model-6-0-features-for-direct3d-12.md)
</dt> <dt>
[Shader Model 6](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/shader-model-6-0.md)
</dt> </dl>
</pre>
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