<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/99208>99208</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
Implement the `WaveMultiPrefixBitAnd` HLSL Function
</td>
</tr>
<tr>
<th>Labels</th>
<td>
metabug,
backend:DirectX,
HLSL,
backend:SPIR-V,
bot:HLSL
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
farzonl
</td>
</tr>
</table>
<pre>
- [ ] Implement `WaveMultiPrefixBitAnd` clang builtin,
- [ ] Link `WaveMultiPrefixBitAnd` clang builtin with `hlsl_intrinsics.h`
- [ ] Add sema checks for `WaveMultiPrefixBitAnd` to `CheckHLSLBuiltinFunctionCall` in `SemaChecking.cpp`
- [ ] Add codegen for `WaveMultiPrefixBitAnd` to `EmitHLSLBuiltinExpr` in `CGBuiltin.cpp`
- [ ] Add codegen tests to `clang/test/CodeGenHLSL/builtins/WaveMultiPrefixBitAnd.hlsl`
- [ ] Add sema tests to `clang/test/SemaHLSL/BuiltIns/WaveMultiPrefixBitAnd-errors.hlsl`
- [ ] Create the `int_dx_WaveMultiPrefixBitAnd` intrinsic in `IntrinsicsDirectX.td`
- [ ] Create the `DXILOpMapping` of `int_dx_WaveMultiPrefixBitAnd` to `166` in `DXIL.td`
- [ ] Create the `WaveMultiPrefixBitAnd.ll` and `WaveMultiPrefixBitAnd_errors.ll` tests in `llvm/test/CodeGen/DirectX/`
- [ ] Create the `int_spv_WaveMultiPrefixBitAnd` intrinsic in `IntrinsicsSPIRV.td`
- [ ] In SPIRVInstructionSelector.cpp create the `WaveMultiPrefixBitAnd` lowering and map it to `int_spv_WaveMultiPrefixBitAnd` in `SPIRVInstructionSelector::selectIntrinsic`.
- [ ] Create SPIR-V backend test case in `llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveMultiPrefixBitAnd.ll`
## DirectX
| DXIL Opcode | DXIL OpName | Shader Model | Shader Stages |
| ----------- | ----------- | ------------ | ------------- |
| 166 | WaveMultiPrefixOp | 6.5 | ('library', 'compute', 'amplification', 'mesh', 'pixel', 'vertex', 'hull', 'domain', 'geometry', 'raygeneration', 'intersection', 'anyhit', 'closesthit', 'miss', 'callable', 'node') |
## SPIR-V
# [OpGroupNonUniformBitwiseAnd](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpGroupNonUniformBitwiseAnd):
## Description:
A bitwise and [group operation](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Group_Operation) of all *Value*
operands contributed by active [invocations](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Invocation) in the
[group](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Group).
*Result Type* must be a scalar or vector of [*integer
type*](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Integer).
*Execution* is a [*Scope*](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Scope_-id-) that identifies the group of
invocations affected by this command. It must be **Subgroup**.
The identity *I* for *Operation* is ~0. If *Operation* is
**ClusteredReduce**, *ClusterSize* must be present.
The type of *Value* must be the same as *Result Type*.
*ClusterSize* is the size of cluster to use. *ClusterSize* must be a
scalar of [*integer type*](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Integer), whose *Signedness* operand is 0.
*ClusterSize* must come from a [*constant
instruction*](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#ConstantInstruction). Behavior is undefined unless
*ClusterSize* is at least 1 and a power of 2. If *ClusterSize* is
greater than the size of the [group](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Group), executing this instruction
results in undefined behavior.
[Capability](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Capability):
**GroupNonUniformArithmetic**, **GroupNonUniformClustered**,
**GroupNonUniformPartitionedNV**
[Missing before](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Unified) **version 1.3**.
<table>
<colgroup>
<col style="width: 12%" />
<col style="width: 12%" />
<col style="width: 12%" />
<col style="width: 12%" />
<col style="width: 12%" />
<col style="width: 12%" />
<col style="width: 12%" />
<col style="width: 12%" />
</colgroup>
<thead>
<tr>
<th>Word Count</th>
<th>Opcode</th>
<th>Results</th>
<th>Operands</th>
<th></th>
<th></th>
<th></th>
<th></th>
</tr>
</thead>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p>6 + variable</p></td>
<td class="tableblock halign-left valign-top"><p>359</p></td>
<td
class="tableblock halign-left valign-top"><p><em><id></em><br />
<em>Result Type</em></p></td>
<td class="tableblock halign-left valign-top"><p><a
href="#ResultId"><em>Result <id></em></a></p></td>
<td class="tableblock halign-left valign-top"><p><a
href="#Scope_-id-"><em>Scope <id></em></a><br />
<em>Execution</em></p></td>
<td class="tableblock halign-left valign-top"><p><a
href="#Group_Operation"><em>Group Operation</em></a><br />
<em>Operation</em></p></td>
<td
class="tableblock halign-left valign-top"><p><em><id></em><br />
<em>Value</em></p></td>
<td class="tableblock halign-left valign-top"><p>Optional<br />
<em><id></em><br />
<em>ClusterSize</em></p></td>
</tr>
</tbody>
</table>
## Test Case(s)
### Example 1
```hlsl
//dxc WaveMultiPrefixBitAnd_test.hlsl -T lib_6_8 -enable-16bit-types -O0
export int4 fn(int4 p1, uint4 p2) {
return WaveMultiPrefixBitAnd(p1, p2);
}
```
## HLSL:
## Syntax
```syntax
any_int<> WaveMultiPrefixBitAnd(any_int<> value, uint<4> mask);
```
## Type Description
| Name | [**Template Type**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3dhlsl/dx-graphics-hlsl-data-types.md)| [**Component Type**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3dhlsl/dx-graphics-hlsl-data-types.md) | Size |
|-------|--------------------------------------------------------------------|----------------------------------------------------------------------|------|
| *ret* | [**scalar**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3dhlsl/dx-graphics-hlsl-scalar.md), [**vector**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3dhlsl/dx-graphics-hlsl-vector.md), or [**matrix**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3dhlsl/dx-graphics-hlsl-matrix.md) | [**int**](../WinProg/windows-data-types), [**int16_t**](https://github.com/microsoft/DirectXShaderCompiler/wiki/16-Bit-Scalar-Types), [**int64_t**](../WinProg/windows-data-types), [**uint**](../WinProg/windows-data-types), [**uint16_t**](https://github.com/microsoft/DirectXShaderCompiler/wiki/16-Bit-Scalar-Types), or [**uint64_t**](../WinProg/windows-data-types) | any |
| *value* | [**scalar**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3dhlsl/dx-graphics-hlsl-scalar.md), [**vector**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3dhlsl/dx-graphics-hlsl-vector.md), or [**matrix**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3dhlsl/dx-graphics-hlsl-matrix.md) | [**int**](../WinProg/windows-data-types), [**int16_t**](https://github.com/microsoft/DirectXShaderCompiler/wiki/16-Bit-Scalar-Types), [**int64_t**](../WinProg/windows-data-types), [**uint**](../WinProg/windows-data-types), [**uint16_t**](https://github.com/microsoft/DirectXShaderCompiler/wiki/16-Bit-Scalar-Types), or [**uint64_t**](../WinProg/windows-data-types) | any |
| *mask* | [**vector**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3dhlsl/dx-graphics-hlsl-vector.md) | [**uint**](../WinProg/windows-data-types) | 4 |
## Minimum Shader Model
This function is supported in the following shader models.
|Shader Model | Supported|
|-------------|----------|
|[Shader Model 6.5](https://microsoft.github.io/DirectX-Specs/d3d/HLSL_ShaderModel6_5) and higher shader models | yes |
## Shader Stages
* **Library Shader**
* [**Compute Shader**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3d11/direct3d-11-advanced-stages-compute-shader.md)
* [**Amplification Shader**](https://microsoft.github.io/DirectX-Specs/d3d/MeshShader.html#amplification-shader-and-mesh-shader)
* [**Mesh Shader**](https://microsoft.github.io/DirectX-Specs/d3d/MeshShader.html)
* [**Pixel Shader**](../direct3dhlsl/dx-graphics-hlsl-writing-shaders-9.md#pixel-shader-basics)
* [**Vertex Shader**](../direct3dhlsl/dx-graphics-hlsl-writing-shaders-9.md#vertex-shader-basics)
* [**Hull Shader**](https://learn.microsoft.com/en-us/windows/uwp/graphics-concepts/hull-shader-stage--hs-)
* [**Domain Shader**](https://learn.microsoft.com/en-us/windows/uwp/graphics-concepts/domain-shader-stage--ds-)
* [**Geometry Shader**](https://learn.microsoft.com/en-us/windows/uwp/graphics-concepts/geometry-shader-stage--gs-)
* [**Raygeneration Shader**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3d12/ray-generation-shader.md)
* [**Intersection Shader**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3d12/intersection-shader.md)
* [**Anyhit Shader**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3d12/any-hit-shader.md)
* [**Closesthit Shader**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3d12/closest-hit-shader.md)
* [**Miss Shader**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3d12/miss-shader.md)
* [**Callable Shader**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3d12/callable-shader.md)
* **Node Shader**
## See also
- [**Intrinsic Functions (DirectX HLSL)**](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/../direct3dhlsl/dx-graphics-hlsl-intrinsic-functions.md)
- **See [WaveMultiPrefix*() Functions](https://microsoft.github.io/DirectX-Specs/d3d/HLSL_ShaderModel6_5#wavemultiprefix-functions)**
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzsW1tv2zjT_jXMDSFBpmInuciF7NTdAE1bNN3u3gWUOLb4hSIFknLivfh--wuSsiSfkh42bRZoECAWT_PMM8PRkJ5QY_hSAlyi8RSNr05oY0ulLxdU_6OkOMkVW19GGI2nGI2v8HVVC6hAWowmyV90BTeNsPyjhgV_nHKbSYYmCS4ElUucN1xYLhGZoSTrl3jH5f3Xz8YP3JZueCmMuOPSai4NL0xcokmytW7GGDZQUVyUUNwbvFD6STFWue6ZG_zHu9t30yBv3sjCciVnVAg3iks36hYq6kdyuYyLuj4ku1AMliC_Uu6bituB2DePte7Fzd62zc_JsmCsaVf0tCEyd22IzGeKwVuQTgYi85ZNg8j8ILDY0XuU0SfEOGZaGR7z9XEZEWittDkoaqaBWsC2BCeDS3vHHu-OUti5QcvXdecWV1xDYf-OLXtawtXf1-8-1De0rrlcuiXV4msEW4XdsNFk0hvLLfWsvMOkBxejkh0dctdyFkYGOwSxQqyqPWsjMm8ZQGT-PMemXn0Pybcfrz99OaDytcS-61oaqxu_jW5BQGGVdo6Mi-cpcYKFegDN5dITU9EaY25b5_sK0H67HkGB0gylmfFPnTpoksSHeHKLRF9wTot7kMxzjwtq4Bn-vWxE5s7Loz5eHd14ot0L7pekiKR4Y8HQdjbDzsPwh9ptejx4fk-r8HxbUgYa3ygGYthwa-kSjGtpF4r6H_zM835DNFhoNJn4_h2VPtS-dRKP_V9EzhE5EzzXVK8ROUPEtZ0VqqobC30DrWrBF7ygzlZ9cwWm7J9q_giif1yBtvDYP5eNGPQyVVE-WGoJqgI7BKHpegkS9I5MLi1oA8V2K5XrktuBBkIZMHarreLGDEZQIWguBkpKxcLTxYbHzuDB07om54gf6rdaNfV7Jf-UfKF0NeX2gRtwbj6-QuS8tLY2zp_JHJG5hiU3Vq_j-1IrqUys9LL1xcg5o6nBu2Aj-YIDG238NC5tJRBJnxJHLpyYLQcFU2hee458F8YoyTKch0khoI2nS7ckVvWG5BfA7VHffehEkAsXyKkQGJHsCxUNIOIAehCSGVwotyPzxgLD-RrTwvIVOLBcrlRwQPMSQK-75R1GLl0QdIS2LL0YN4hcxHhjIUSyT2AaYfHnde2YwVVjLM4BU2wKKqjGSuOVD5X-hTieIpK5LbEEjZLMhlkvw08QsgP3zSMUTWAtw9xg2mK6LdSLQfFr30WcRc5UtqQWcwbSutHGv7xax16gJBu4DaaLBRStY9mSO2erKipZjK9tx7QDTbLbJg92908x7nT-XEIrza7d2GunuM8oSTZwc0_G_ycxvl4c6AncIZLNRGMsaGCfgDUFhMYQjzZ9t_yfLU-oNRiQtoXUInKG9w7Rb6pugiPEuDcRNXjPwQaa7YvkgU3D__GLF6HXvekbA_ETGClKso2_7ngp_ik-6ih8KJXx5rx1xycmwYX_DLeRxinn04ojWhSqArzQqupculDSWCqtd6ouc3khVWatsOuhpIsYT6GkK660g99IBgsugeFGCqfdERtSiwVQY_HIB36Ka5e_OcuQjX_uTUJJtvRZlnYbTG75gU8Pf0JcdEaEEF_kMmzYIfFJpr0r-3y75yJvGYrbN-J4OqM1zbngdv0ilupX9y9i3G3unTd2prktK7C82Nrm-wO7oNCNO7bkR6otd2QAe_8ljOjCAhpPb7gxjrocFkrDSyj_Z2j3OZMXvwJtuJJ4FKdt6GzNkM6sT7fSN-GpUCI40KABG7t2Q64QIQ-c2dLROSKIjBEh2CH-PfiHByMy3-PelkBZ_6QHHSh985fSDM9UI22Y7hsH_eHgc7gvvG3MsYkh6Tvc-wKt7klvPW0rniu2PkgDw4WgxgR-vSPnQhX3uKSCL2UkYGHxKny2qkaEBOmO4QlGZIpXVPPg_05s3YNj_4qQdHzx5Mooyb57bZTOoHJ_yURYlE45Q2SydJ-CoNCZznK95We-eZhsbA1-CRJQOnOJR6lhEaYjkgYA16wbOIT1nEaIzOnPhTtMbYeAffs34D1kiz5V_yWW2DsJDvXznbjv_Aa1jk96ZXshJOYvzv0Hf-yn4giK70E-zA6_Cv9-nN2KrK5hkAwk25cXn8FYPKMGEDk3LqfynSGt8SPcoDePtKoF4JHrnSTh199bJ21qwx6L3duv9sbWgrH-jhtHn7Hg-d3k7hxHIB2kaDTJuY3cIcXg6EN77wePtdIWc2lP8UIicu4_1SOXwjXhMwn3RlMHU4NttDwsHZHzMM_PcPQnGTq7GqrRU-Hv7Xfudm7X0tLHnrTNLLNpp3J9x8O7On1zFMT2qFU4NAZtUDo7dY0VNfc9xiG6LXO5o-fwwqm7FfXXn-Ge0R-gEMk-Q1ULamFz_DxyelpyWzZ5XKgKkfkNL7QyamGvlM9FH7hMCSLzXKjc2Tm0MjD3VtWR0UVrf39JmzLvFGQex_tt7DFaalqXvDCRvw1m1NJg-7jy92pD7DNV1UqCtP8R8OGi2Z3Zumvh9p64__RDP__SMoOF-vtrRDIN1p1ntmwQLhVeH_cBV-s0ZAA43NW9PsABVw9Y6R5zRa3mj68Pc8A1cO4OsQtaA7h-tb-4_KjVMkBi6sEMNsiulbi0o8md_UqVq43K_Zd54fscFyG4AO1l3nNE5qNJNOU2uvXuEX0-Intyevdj-JsfJaD5BQwMXa75Tha8G1C5xluRY7W5Av0dO37Hjt-x43fs-IbYEZLendDxX9iJ24i_x6p-hdO9L79vuORVU20VMYQBn0tu8KKtx8LcYNPU7qAErP0CFS-UEOqByyU2YXblZps48L1bFoGSi9vNCrs564GUsxuCxtOtpSbx-JCVOs-LW3tx1ftgdNtedbOUITJ3J6-7sKhfc3I3dgxRyXDJlyXobYU8deu-lKM_rQ0LPTY9WXtZ_i4UXrSDWnO1A4anjsbC9phf4IKj0eAhGo0iylZUFsAi43WL2qKRKPDSvh12lMmGdSTPqvQt9roBU4b1Nl9NbNWstKgiKllUgSnb5wMQ3UIvi2xP5Ef-COKAzK8KAQ-aWy6XrUImuvDMp74YZ6N1TkOB057kL75G518WHQp_npX9RyMOKb1NtACqZdzTHdwbZNSYPoohMm8earcHNvAKJQuorespG9Hx4D01ikoTHcBz5SuSfgKiUPq0g4kdxPS2rYr6Cag2BVg7uJYHcX0a1mb9-tDk5mu6jnpMT0ah60EJ2esAPyxqezqA-jq31wGaynVUcvsk3llXh_c6MLd1gc_ivuHGvA7EFTfmaYrbQsbXAXdTVnkQsof2XjHYy3i2UiYATIVRXXu0tXXbkufNvwEYjMh5--YN9-XuhPDaEvWuzDjapMumoybalJyBL6vZubD3fecu9-w0fpHcNn2gK6ic3NrL7YF2hJ6wy5RdpBf0BC5HZ2Q0miTn55OT8pKNC5aSvGAERknKLkajUX7K8gmcJnk-WYxO-CVJyGlyNpqQZHR6OonHizGDUzJhZ3kxTpIFOk2golzEQqyqWOnlCTemgcuLC5KcnwiagzD-_18IqcDSvFn6LxVniJC2_BulWVdY3_YEb9gbtilu2XQoi9JsM3Z8daIvHYgob5YGnSaCG2t6WJZbAZf9P9k8Vyrv1u0sd9JocfmEQ7YV6158rdX_QeEOyZ4JZ71AxuqS_C8AAP__NlztBQ">