<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/99076>99076</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Implement the `AllMemoryBarrier` HLSL Function
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            metabug,
            backend:DirectX,
            HLSL,
            backend:SPIR-V,
            bot:HLSL
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          farzonl
      </td>
    </tr>
</table>

<pre>
    - [ ] Implement `AllMemoryBarrier` clang builtin,
- [ ] Link `AllMemoryBarrier` clang builtin with `hlsl_intrinsics.h`
- [ ] Add sema checks for `AllMemoryBarrier` to `CheckHLSLBuiltinFunctionCall` in `SemaChecking.cpp`
- [ ] Add codegen for `AllMemoryBarrier` to `EmitHLSLBuiltinExpr` in `CGBuiltin.cpp`
- [ ] Add codegen tests to `clang/test/CodeGenHLSL/builtins/AllMemoryBarrier.hlsl`
- [ ] Add sema tests to `clang/test/SemaHLSL/BuiltIns/AllMemoryBarrier-errors.hlsl`
- [ ] Create the `int_dx_AllMemoryBarrier` intrinsic in `IntrinsicsDirectX.td`
- [ ] Create the `DXILOpMapping` of `int_dx_AllMemoryBarrier` to  `80` in `DXIL.td`
- [ ] Create the  `AllMemoryBarrier.ll` and `AllMemoryBarrier_errors.ll` tests in `llvm/test/CodeGen/DirectX/`
- [ ] Create the `int_spv_AllMemoryBarrier` intrinsic in `IntrinsicsSPIRV.td`
- [ ] In SPIRVInstructionSelector.cpp create the `AllMemoryBarrier` lowering and map  it to `int_spv_AllMemoryBarrier` in `SPIRVInstructionSelector::selectIntrinsic`.
- [ ] Create SPIR-V backend test case in `llvm/test/CodeGen/SPIRV/hlsl-intrinsics/AllMemoryBarrier.ll`

## DirectX

| DXIL Opcode | DXIL OpName | Shader Model | Shader Stages |
| ----------- | ----------- | ------------ | ------------- |
| 80 | Barrier | 6.0 | () |

## SPIR-V

# [OpMemoryBarrier](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpMemoryBarrier):

## Description:
  
Control the order that memory accesses are observed.  
  
Ensures that memory accesses issued before this instruction are observed
before memory accesses issued after this instruction. This control is
ensured only for memory accesses issued by this
[invocation](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Invocation) and observed by another invocation executing
within *Memory* scope. If the **Vulkan** [memory model](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Memory_Model)
is declared, this ordering only applies to memory accesses that use the
**NonPrivatePointer** [memory operand](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Memory_Operands) or
**NonPrivateTexel** [image operand](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#Image_Operands).  
  
*Semantics* declares what kind of memory is being controlled and what
kind of control to apply.  
  
To execute both a memory barrier and a control barrier, see
[**OpControlBarrier**](https://registry.khronos.org/SPIR-V/specs/unified1/SPIRV.html#OpControlBarrier).

<table>
<colgroup>
<col style="width: 25%" />
<col style="width: 25%" />
<col style="width: 25%" />
<col style="width: 25%" />
</colgroup>
<thead>
<tr>
<th>Word Count</th>
<th>Opcode</th>
<th>Results</th>
<th>Operands</th>
</tr>
</thead>
<tbody>
<tr>
<td class="tableblock halign-left valign-top"><p>3</p></td>
<td class="tableblock halign-left valign-top"><p>225</p></td>
<td class="tableblock halign-left valign-top"><p><a
href="#Scope_-id-"><em>Scope &lt;id&gt;</em></a><br />
<em>Memory</em></p></td>
<td class="tableblock halign-left valign-top"><p><a
href="#Memory_Semantics_-id-"><em>Memory Semantics
&lt;id&gt;</em></a><br />
<em>Semantics</em></p></td>
</tr>
</tbody>
</table>



## Test Case(s)

 
 ### Example 1
```hlsl
//dxc AllMemoryBarrier_test.hlsl -T lib_6_8 -enable-16bit-types -O0

export void fn() {
    return AllMemoryBarrier();
}
```
## HLSL:

Blocks execution of all threads in a group until all memory accesses have been completed.

## Syntax

``` syntax
void AllMemoryBarrier(void);
```

## Parameters

This function has no parameters.

## Return value

This function does not return a value.

## Remarks

A memory barrier guarantees that outstanding memory operations have completed. Threads are synchronized at GroupSync barriers. This may stall a thread or threads if memory operations are in progress.

### Minimum Shader Model

This function is supported in the following shader models.



| Shader Model                                                                | Supported |
|-----------------------------------------------------------------------------|-----------|
| [Shader Model 5](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/d3d11-graphics-reference-sm5.md) and higher shader models | yes       |



 

This function is supported in the following types of shaders:



| Vertex | Hull | Domain | Geometry | Pixel | Compute |
|--------|------|--------|----------|-------|---------|
|        |      |        |          |       | x       |



 

## See also

<dl> <dt>

[Intrinsic Functions](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/dx-graphics-hlsl-intrinsic-functions.md)
</dt> <dt>

[Shader Model 5](https://github.com/MicrosoftDocs/win32/blob/docs/desktop-src//direct3dhlsl/d3d11-graphics-reference-sm5.md)
</dt> </dl>
</pre>
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