<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/98474>98474</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Machine verifier failure because of register-coalescer - involving sub-registers
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          petar-avramovic
      </td>
    </tr>
</table>

<pre>
    When register-coalescer merges small registers into big, some sub-registers end up being undefined in some paths.
[short.mir.txt](https://github.com/user-attachments/files/16177318/short.mir.txt)
[short.ll.txt](https://github.com/user-attachments/files/16177319/short.ll.txt)

llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs short.ll -o - 
llc -march=amdgcn -mcpu=gfx1010 -run-pass=register-coalescer -start-before=register-coalescer -verify-machineinstrs short.mir -o - 

llc -march=amdgcn -mcpu=gfx1010 -run-pass=register-coalescer -debug short.mir -o - 

```
      bb.0:
        successors: %bb.2(0x50000000), %bb.1(0x30000000)
        liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4

        %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
        %1:sreg_32 = COPY $sgpr4
 S_CMP_EQ_U32 killed %1, 0, implicit-def $scc
        S_CBRANCH_SCC0 %bb.2, implicit killed $scc

      bb.1:
        successors: %bb.3(0x80000000)

        %2:vgpr_32 = IMPLICIT_DEF
 %3:vgpr_32 = IMPLICIT_DEF
        %4:vgpr_32 = IMPLICIT_DEF
 %5:vgpr_32 = IMPLICIT_DEF
        S_BRANCH %bb.3

      bb.2:
 successors: %bb.3(0x80000000)

        %6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
        %7:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %6, killed %0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
        %2:vgpr_32 = COPY %7.sub0
 %3:vgpr_32 = COPY %7.sub1
        %4:vgpr_32 = COPY %7.sub2
 %5:vgpr_32 = COPY killed %7.sub3

      bb.3:
        EXP_DONE 0, killed %2, killed %3, killed %4, killed %5, -1, 0, 15, implicit $exec
 S_ENDPGM 0
```


$ llc -march=amdgcn -mcpu=gfx1010 -o - short.mir -run-pass=register-coalescer -debug

In short.mir Register Coalescer tries to combine registers %2:vgpr_32, %3:vgpr_32, %4:vgpr_32, %5:vgpr_32 with %7:vreg_128.
In bb.1, instructions:

    %2:vgpr_32 = IMPLICIT_DEF
    %3:vgpr_32 = IMPLICIT_DEF
    %4:vgpr_32 = IMPLICIT_DEF
    %5:vgpr_32 = IMPLICIT_DEF

are converted to only one instruction. %2 in %7:sub0 are merged and first instruction is updated to:

    undef %7.sub0:vreg_128 = IMPLICIT_DEF

but after others get merged their IMPLICIT_DEFs get deleted.

```
      bb.0:
 successors: %bb.2(0x50000000), %bb.1(0x30000000)
        liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
      
        %0:sgpr_128 = COPY $sgpr0_sgpr1_sgpr2_sgpr3
        %1:sreg_32 = COPY $sgpr4
 S_CMP_EQ_U32 %1, 0, implicit-def $scc
        S_CBRANCH_SCC0 %bb.2, implicit killed $scc
      
      bb.1:
        successors: %bb.3(0x80000000)
      
        undef %7.sub0:vreg_128 = IMPLICIT_DEF
        S_BRANCH %bb.3
      
      bb.2:
 successors: %bb.3(0x80000000)
      
        %6:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
        %7:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN %6, %0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
      
      bb.3:
        EXP_DONE 0, %7.sub0, %7.sub1, %7.sub2, %7.sub3, -1, 0, 15, implicit $exec
        S_ENDPGM 0
```


in path bb.0 -> bb.1 -> bb.3 %7.sub1, %7.sub2, %7.sub3 are undefined. This does not cause Machine Verifier failure(yet).  
Tail Duplication moves EXP_DONE from bb.3 into bb.2 and more importantly bb.1:

```
    # After Tail Duplication
    # Machine code for function test: NoPHIs, TracksLiveness, NoVRegs, TracksDebugUserValues

 bb.0:
      successors: %bb.2(0x50000000), %bb.1(0x30000000); %bb.2(62.50%), %bb.1(37.50%)
      liveins: $sgpr4, $sgpr0_sgpr1_sgpr2_sgpr3
      S_CMP_EQ_U32 killed renamable $sgpr4, 0, implicit-def $scc
      S_CBRANCH_SCC0 %bb.2, implicit killed $scc

 bb.1:
    ; predecessors: %bb.0

      renamable $vgpr0 = IMPLICIT_DEF
      EXP_DONE 0, killed renamable $vgpr0, renamable $vgpr1, renamable $vgpr2, renamable $vgpr3, -1, 0, 15, implicit $exec
 S_ENDPGM 0

    bb.2:
    ; predecessors: %bb.0
      liveins: $sgpr0_sgpr1_sgpr2_sgpr3
      renamable $vgpr0 = V_MOV_B32_e32 0, implicit $exec
      renamable $vgpr0_vgpr1_vgpr2_vgpr3 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed renamable $vgpr0, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)
      EXP_DONE 0, killed renamable $vgpr0, renamable $vgpr1, renamable $vgpr2, renamable $vgpr3, -1, 0, 15, implicit $exec
      S_ENDPGM 0

    # End machine code for function test.
```


This causes machine verifier to fail for $vgpr1, $vgpr2, $vgpr3

*** Bad machine code: Using an undefined physical register ***
- function:    test
- basic block: %bb.1 (0x569b4a93c240)
- instruction: EXP_DONE 0, killed renamable $vgpr0, renamable $vgpr1, renamable $vgpr2, renamable $vgpr3, -1, 0, 15, implicit $exec
- operand 2:   renamable $vgpr1an undefined physical register ***
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzMWVtzozgW_jXyyykoEODLgx8SX3ZS1blsks707Asl4NjWNiCXJDzJv9-ScAwYJ3G2u6Y75ZIjJH06N33nyDCl-LpEnJLokkTzAav0RsjpFjWTDttJVogdTweJyF6mf26wBIlrrjRKJxUsR5WihALlGhWoguX5YVwBL7WAhK8JnYESBYKqEqcZxjKDagsJ8nINVZnhipeYAS_ryVumN8ol3px4FyS6VBshtVtw6epnTaI5oeON1ltFggtCl4Qu11xvqsRNRUHoslIoHaY1SzcFlloRulzxHM23P_RHo8AfE7rsYtLJ0WZ5_pP2mhz22kMetrJtnqfgFEymGxLMWZGt0xKcIt1WJJivV8--53vg7FDy1YtTsHTDS-Sl0lLBKyg4Ahz4BJqsSmfLlCLB_IQ_HaWZ1E6CKyHxjSnvyFNw2Rbo54mVYVKt39uEDL39x3bB_iWJ6xnPtR4BqCpNUSkhjVOB0ChJXEro2HuOvPrPOInO9kO-HQpaQx20nO-MCWqoUK230otN69uW2jao0exo2Bb6FYTQyMhpxmOfjoEEc5jd3v31HuQxgG8AJK7jgPbW7zeFh3h2fRcv_h1_DSh853mOWb2UzsAzDS-2OU-5djJc2cVp2t3oIZ5d3l_czP6IH2Yzr7Fes7TBbVYf-cQ_yyeBNfz42PA9xSkJLnbGcnvFr67vvlzNrh7j-WK5n0xoFHw8q4EMz4KMzoZ8iGujHTQ7ZRXaWOVHzDE8kuopvr59ii8DGmNAu142PsJnTHsYI4NhYuk1GC-_LpeL-_jL7cU8Xt7eX188xt_--s-f8dX82-KmFUlDA990vUNgHTXHEoDR3ao6zlDiCiWWKbIkR8gFM1hjEsxCeAYVUBIs9ieU5Xxdgg1flmVSbVmKMO6d0RNBsj8d0chVVeK9HSadef6HgdKZTt8OFTuvsZOdfjoqgt5ZWXy7i-e3N4vakg0I7XaDbjfsdiPTdZqD70fvBMZDvLiZ3_3rGryTXNtpaQhn8b3h7xadn0P_7X2uytbq-_0KmB1WaMlRgRaQiiLhJbZqk2407Ik-6D0Je0_aTvyb683xSXEPotVpYwY2N1ap5sJmiGMHn0de9cTz-Os87qonfkxfdcskQirKHUqNmTGpKPMXECW21XOtMqaC2xvFHCswS22FmAErM1hxqXR7FXAF1TZjNfAJC9nasHVOj2jpLZGTSgNbmYgQemN8vkb9KojeIJedlfVwhjlqzNxPFhW_RTWx56NfX1P8E8VEX9kfLSlOme_Tkfd-rj8p9P-X8d9w9i_I-68J_3fJ9J9MnY1zWx2_3aHtTvCZlHkIhrMzJy_tvdfSCzgkWNiwPvwXnCOhJdzDfdqFxw1XkAlUUAoNKasUwnV9bYMnc4vjKGHFeF5JJHT8guZ-6r4a8pHxHOaV0Y9Zti7EDlVjxJUURS1afd1PXGppvhASjV2E1KzU-Uv3fL7JrIQGcGFJ-3jj7pxXBVKRIayEhFVV1tlEo9Imtm7E3R9XyljmUbL0u_rCd1iisk9uxNM9rluDc1NafFUon1heoepkoBP3xx_m--CytWpIXXN0ot6aYNQMtHbv54ewlQ0-oPRTtz-JJSvs6WvjnUPfP3QT7DG2MctWYoY943r9srgjtOE8711OPlkw9zHMYO-pf_IpPfn0UwTRY4aDwN3EcI5tPlM7fGzGTyaOPkpsDWdbatvg_Dvkabe8FaxvFEe_Og_9lgF3Oh91mHVhyPtddnU_TGM25dhMow5Yu9dUo4XNNha3rW9by4NunVvl_gOXrCuiceFXxcs1sLL1S_J286J4ypqfpOEAUSM6B70MAkCdO_ZDCVM8hSQX6ffmrPlQs_xwkoRsEqQ0bEoyp32pMUt-xwhwQGxRmgRNa537O59rw0E2DbJJMGEDnPoj6o08GoWTwWYaTuhqiEHkZ5EX0RXNsvGIBePQx2DMcDwc8Cn1aOiNfN-nURROXDbxs_GQ-XSSjhkbMRJ6WDCeu3m-K1wh1wOuVIXTyTgchYOcJZgr-8KC0hL_BjtIKCXRfCCnZo2TVGtFQi_nSqsGRXOd4_T6OCL3xQ8kWFdHYnXqLYfx707kOxNnnTcZg0rm03deEJjt91_OVor_YqoJXVqhFaHLWqndlP4vAAD__2FxO2k">