<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/97943>97943</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [Hexagon]Enhance the handling of addrspacecast conversions.
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          DigOrDog
      </td>
    </tr>
</table>

<pre>
    # Description
The below IR code compiles successfully on various architectures including AArch64, x86_64, ARM, Berkeley Packet Filter (BPF), NVIDIA Parallel Thread Execution (NVPTX64), PowerPC, and RISC-V64. However, it encounters compilation issues specifically on the Hexagon architecture. There is a consideration of whether it is essential to strengthen the handling of such cases to ensure compatibility and robustness across all targeted architectures.
https://godbolt.org/z/ja8W85Pjv
# IR
llc in.ll -mtriple=hexagon -mcpu=generic -mattr=+nvs
```
define double @f(ptr %G, ptr %x) {
BB:
  %Castaddrspacecast = addrspacecast ptr %x to ptr addrspace(1)
  store ptr addrspace(1) %Castaddrspacecast, ptr %G, align 8
  ret double 0.000000e+00
}
```

</pre>
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