<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/97909>97909</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Suboptimal codegen for `sdiv` by constants
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:AArch64,
            backend:X86,
            missed-optimization
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Kmeakin
      </td>
    </tr>
</table>

<pre>
    GCC is able to generate shorter code for signed division by non-power of 2 constants than clang:
https://godbolt.org/z/axeTh4qb8

AArch64, clang:
```asm
sdiv3:                                  // @sdiv3
 mov     w8, #21846                      // =0x5556
        movk    w8, #21845, lsl #16
        smull   x8, w0, w8
        lsr     x9, x8, #63
        lsr     x8, x8, #32
        add     w0, w8, w9
 ret
```

AArch64, GCC:
```asm
sdiv3:
        mov     w1, 21846
        movk    w1, 0x5555, lsl 16
        smull   x1, w0, w1
 lsr     x1, x1, 32
        sub     w0, w1, w0, asr 31
 ret
```

x86-64, clang:
```asm
sdiv3: # @sdiv3
        movsxd  rax, edi
        imul    rax, rax, 1431655766
        mov     rcx, rax
        shr     rcx, 63
 shr     rax, 32
        add     eax, ecx
 ret
```

x86-64, GCC:
```asm
sdiv3:
        movsx   rax, edi
        sar     edi, 31
        imul    rax, rax, 1431655766
 shr     rax, 32
        sub     eax, edi
        ret
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJycVU2TsygQ_jV4oZJCUCIHD9mkMoc97h72CsJEdlDyAmac-fVvgUkmH-U7H1YKIv30092Prc291_teqRqUf4Fym_EhtNbVf3eKv-g-E1a-1U-bDdQecmEUDBbuVa8cDwr61rqgHGysVPDZOpioJJT6qL22PRRvsLf94mBflYP2GWLY2N4H3gcPQ8t72Bje7wFZA7QFaN2GcPDxDu8A3u2tFNaEpXV7gHfvAO_4qP5ti1-imuDTul67pqUFwJs7NkDR9OO-m0681EcCyBp-ek0ZQFCgySe5w84ek_W1itEAJjivCvpnBrJFY1mW9ERxujp7fHlgKuN_4028z-8cfDcYAyEck8MrSmt1izHepX1k0TqeqSmZgVU3MIJvYVzKqdhzrLiyE8apcCfyzCN52my-8EAexJki55EhaTyjXgIkfS_azQqXXwmXnzAXKZJxWu918IO41uGKhnsHSf4lRcaKLr7ZowCT-_77KN-PEkLHx8iopL61626IFZ_tpy0vSE7LckUfxUy7ay7o2_pbd22_dNPlfKKfax91SrIZvynUDzvHj3BeGc-nnKMh5pz_SLhPKj83jJpJ4lGATNZEMsJ4pup8hRFmFDGatbUiAolCVIiW1YpjXuWrlaBIiYrlrJRNpmuMcIFWiGKEclIuG8QkQYoxUaGybHJQINVxbZbGHLv4Kc2094Oq2YohlhkulPHp04-x4M2L6iUgH-8vBnhzY_mvopfTTnuv5MIegu70Ow_a9tFWbjNXx2gLMew9KJDRPviP-EEHo-p_BpEcuUnTY6_6NEAATQ0PKIqz4zIsssGZ-m466NAOYtnYDuBdJD9ti4Oz_6smALxLlXqAd1Oxxxr_DgAA__-1R8xw">