<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/97821>97821</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [AArch64] Get different assemble for code which doesn't use sve register 
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          vfdff
      </td>
    </tr>
</table>

<pre>
    * test: https://gcc.godbolt.org/z/Mn6ob7efq
```
#define difference_type long long

void foo1();
extern long long __begin_, __first_;

int foo (long long a[]) {
   if (__begin_ > __first_) {
 difference_type __d = __begin_ - __first_;
            __d = (__d + 1) / 2;
            __begin_ -= __d;
   }
   return 0;
}
```
* the above code split from **llvm-project/libcxx/include/__split_buffer**, we can see the final assemble doesn't include sve register, but it generate different assemble for code with/without **+sve**. For the sve version, it even use a **sdiv** instruction for **__d = (__d + 1) / 2;**

> with sve
```
foo:                                    // @foo
        adrp x8, :got:__begin_
        adrp    x10, :got:__first_
        ldr x8, [x8, :got_lo12:__begin_]
        ldr     x10, [x10, :got_lo12:__first_]
        ldr     x9, [x8]
        ldr     x10, [x10]
        subs    x10, x9, x10
        b.le    .LBB0_2
 add     x10, x10, #1
        mov     x11, #-2                        // =0xfffffffffffffffe
        sdiv    x10, x10, x11
        add     x9, x10, x9
        str     x9, [x8]
.LBB0_2:
        mov     w0, wzr
        ret
```
> without sve
```
foo: // @foo
        adrp    x8, :got:__begin_
        adrp x10, :got:__first_
        ldr     x8, [x8, :got_lo12:__begin_]
 ldr     x10, [x10, :got_lo12:__first_]
        ldr     x9, [x8]
 ldr     x10, [x10]
        subs    x10, x9, x10
        b.le .LBB0_2
        add     x11, x10, #1
        add     x12, x10, #2
 cmp     x11, #0
        csinc   x10, x12, x10, lt
        sub x9, x9, x10, asr #1
        str     x9, [x8]
.LBB0_2:
        mov w0, wzr
        ret
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJy0Vs2SqzYTfRp50zUuaIx_Fizs649vkzwDBajBSsmSIwnG9z59SvwMYM9kXKmEmgKMTp_TLR2NOrdW1IooYfGJxedV3riLNklb8apaFZr_TBgewZF1LDrCxbmbZdGRYcowrctyXWteaOnW2tQM018M09_VVhc7qv5kwZkFR7YNhr_-J0acKqEIuKgqMqRKytzPG4HUqu5uA7C7t1pwqLQOGe4ZHlh06r_T3ZFRUwxkWUG1UBnDH5BllTDWZR_o_i6U81TAcD_F5X3dDA_AdgMcAETlYSMpsOh_E-sC-lhFlnFg0fkjH3h7Tgdm14jv1DgwPEHYKWAK-EXEyNzr8DmK7c4f74ZcYxQE0zSMg09rcgR3IcgL3RKUmhPYmxQOKqOvwNADpGyvbzej_6DSMUylKMr7nWEqVCkbTgzTLOuCsqLxM9JH-dV4JyhzBZaoE6mEyiXk1tK1kARck1UMdw4GJrAtgaFaWOdZfkDROBAOalJkcjf5xk0klTZ92u_CXRim_qEbB2MSJ9tS_76GVJsuDy_TkrFCK68iHFBLChpLkA-Blou2fwOhrDNN6YRWnVr_-dvF6_VnHvRG8tl5-U_XotLab7QXrn4PAtsEPmZhk5ybG9z3vi4WHWvt9-7HBnlGAsA9DB7Qg2cXaMnNSBuf5vyZ1CHOReLzc-RcJz4tFKf4QfbL-MOk_prGI8o2hZ2hekL_Y4Eq1pL8c_3b6RRkOAzmnM8VRiGMwmX0VbcDLhwAb_jdMkbn4F4tL3rInIv2Wd1rPCwpn03VVOaSy309n2PN0fHzqt47xvdfZjlsyH3-32WwvN-Q37j-O0v7hF929euWnvG-auv_1M__upGXLn70SW_SL8084XCJG_nK6-3B7Q85lFaocm7cOZF0T2WNtcwNnFvzSW7_1MYvW3jFk4gfokO-oiTcYRDuo8MmXF0S3G32Vc75riii7bYMIx5WOXIMyqiqwn28EgkGuAl2QRxijBiu4zLeYn7I4922Kni5ZZuArrmQa3-0-v5pJaxtKDns9hiuZF6QtF1XhqjoHbpBhuibNJN0x3HR1JZtAimssxOLE0527dzxaMrLdsPiM_yf3N-fmxdRXmZnsT8F5-cwrBojk4fuT7hLU6xLffX9gGzHx6xL6HK2DNO-pjbBvwIAAP__EXjJAw">