<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/96679>96679</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            Switch clang-cl's sequential consistency reads and writes to match what the latest MSVC generates
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            new issue
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          mcfi
      </td>
    </tr>
</table>

<pre>
    Build the following code on Windows using clang-cl.

```
#include <atomic>
#include <iostream>
#include <thread>
#include <vector>
 
std::atomic<int> cnt = {0};
 
void f()
{
    cnt.load(std::memory_order_seq_cst);
 cnt.store(1, std::memory_order_seq_cst);
    cnt.store(1, std::memory_order_release);
}
```

This was the code generated with `clang-cl -c -O2 --target=aarch64-pc-windows-msvc /FA`. Notice that five dmb ish barriers were inserted.
```
        adrp    x8, "?cnt@@3U?$atomic@H@std@@A"
        mov     w9, #1                          // =0x1
        ldr     wzr, [x8, :lo12:"?cnt@@3U?$atomic@H@std@@A"]
        dmb     ish
        dmb     ish
        str     w9, [x8, :lo12:"?cnt@@3U?$atomic@H@std@@A"]
        dmb     ish
        dmb     ish
        str     w9, [x8, :lo12:"?cnt@@3U?$atomic@H@std@@A"]
        ret
```

Below was the same source code compiled by VS2022 17.6+. As can be seen, acquire load was lowered to ldar and released store was stlr, both are one-way barriers that should be more performant than dmb ishs. In addition, the sequential consistency store was lowered to stlr + dmb, which is 2 instructions, while clang generates dmb + str + dmb, 3 instructions.

```
|void f(void)| PROC                                        ; f
        adrp x8,|std::atomic<int> cnt|
        add         x9,x8,|std::atomic<int> cnt|
        ldar        w8,[x9]
        mov         w8,#1
 stlr        w8,[x9]
        dmb         ish
        stlr w8,[x9]
        ret
```
</pre>
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