<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/96427>96427</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[x86] Invalid assembly given inverted meaning
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
workingjubilee
</td>
</tr>
</table>
<pre>
The following LLVMIR is misassembled:
```llvm
; ModuleID = 'example.1737988f50a8444b-cgu.0'
source_filename = "example.1737988f50a8444b-cgu.0"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
; example::lea_sub
; Function Attrs: nonlazybind uwtable
define i64 @_ZN7example7lea_sub17h65e6a411b5553049E(i64 %x) unnamed_addr #0 {
start:
%y = alloca [8 x i8], align 8
%0 = call i64 asm sideeffect alignstack inteldialect "xor rax, rax\0Alea rax, [rax - 8 * rdx]", "=&{ax},{dx},~{dirflag},~{fpsr},~{flags},~{memory}"(i64 %x), !srcloc !3
store i64 %0, ptr %y, align 8
%_0 = load i64, ptr %y, align 8
ret i64 %_0
}
attributes #0 = { nonlazybind uwtable "probe-stack"="inline-asm" "target-cpu"="x86-64" }
!llvm.module.flags = !{!0, !1}
!llvm.ident = !{!2}
!0 = !{i32 8, !"PIC Level", i32 2}
!1 = !{i32 2, !"RtLibUseGOT", i32 1}
!2 = !{!"rustc version 1.79.0 (129f3b996 2024-06-10)"}
!3 = !{i32 0, i32 106, i32 130}
```
Note that `"xor rax, rax\0Alea rax, [rax - 8 * rdx]"`!
Here is the assembly output from llc:
```asm
example::lea_sub::h65e6a411b5553049: # @example::lea_sub::h65e6a411b5553049
push rax
mov rdx, rdi
xor rax, rax
lea rax, [rax + 8*rdx]
mov qword ptr [rsp], rax
pop rcx
ret
```
Note the `-` in `lea rax, [rax - 8 * rdx]` became a `+` in `lea rax, [rax + 8*rdx]`. The assembly is invalid, but the assembling is incorrect instead of rejecting it.
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJycVs2O4zYMfhrlIjjQj38POSSbTjvA7LbYbnvoJZBt2tGuLLmSnMn00GcvZDuJMzvooA0CWxL5UeRHipZwTrYaYIOSHUr2KzH4o7GbZ2O_Sd1-HUqpAFalqV82X46AG6OUeZa6xU9Pv398_Iylw510wjnoSgU14ltE9ohcnimZ_kqdunmJ7_BHUw8KHvcY8T1GLIOz6HoFa5rxrMjzJiEij-O4jKp2WBPEsgnqzGArODRSgRYdzGj2HppNaC9sCx7XwgslXszgr_ioQ3wLUc8ygviWs_ERpvR-GkZpPD4ieR1QliO-pSyPmpzMIz0upRd4Gke_BrVXrngre3UN45ynhzSOBv1Nm2cdKamHc9Tq4Yq68TdHHMjmWwXi4IbyJn0YdOWl0XjrvXWIb7E2Wom_Xkqpazw8e1EqmNRraKQGLNMYo5gc_vh0SUU2W6XZMU0gFTGlZZIknMTFD4jlI4AlZ8QKPOiQjPog6tpixDjBKNvNCfPC-mtJ4AB5GcMVSplKYJTscnzGMkfJHrEPWCjZapwv1MmoXgmlRieF67CTNUDTQOUnfedF9Q1L7UHVUqiwHtg0FltxDlbDK_lAAlGXJZTsrDjjCOcYsS229Xn0gI0yxhDfI5aibCfOKAueoWxXz8O_w1jaRon2ttD0zi5mSrTuNu2gM_ZlnLN77qbtqLOVMlUY8Uvozhs754UlJOj13o78vc3TYSJKGVEH1DsAC_5i-0Dmwsn2yyoT3ltZDh7cnNJQo9nurUoKhPXWlBCNmbjQx6RWUkMkXIcYC0pT1UdVP1x1znkaBW8ZfrU_YjS0jHU3dor1yOh8UGgoL0bJTB69IWeMrEH7e2X2vXmy0JCc4Xy2hxj75fEDfoITqLkigpgtt6GvsOyG_eyfZPmbgx9__rJA3znJ7n1DjNnB-QqfwLpwbOk6K9YEI5ZTVjS8LIoUM8LiiKRRCLsIhhf2-CtvyHVXkl6HnNwgl6a8ZOST8YD9UXgcBP_7_AQsXdr9CUIdO-yPgOevxAs2g-8HjxtrOqxUdftoXDwLRTOuvNnpxsl3fSk0OsR4aGT_BTUfienXD-4Y3iHMO0FnTmOUgY5aLgO8aATCLtCZtDt5YG8hnxlEbBcqbzsz-IbdsHP4_flsbD0d6mRnXT-3zO_26U0_7VNdBBb8-4mHkPcIpQRLHYbvJjsluIQqfIbFVDK7fwO_ijMla_xlWRHSYalPQsk6gMrBLwsmXDdGhcpYG_q71M6DqLFpsIWvUPlRw69X9YbXBS_ECjY0owXlRU7j1XGTcJFzqGhaJ0XDCS9o3qRVARmjNKcsXclNOGEkZZyShNB4LUQBcV5naSmAiKIJVdUJqdZjizG2XUnnBtgUacyylRIlKDfeoRjT8IxHYTgQyX5lNwETlUPrUEyUdN7drHjp1Xj5OucpSvb4cWLhxkwrT6ADOWA91LgDoaVuV4NVm6P3ffi-I_aA2EMr_XEo15XpEHsY71vTK-qtCRwh9jB65RB7mLw-bdg_AQAA__-31cJl">