<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/95758>95758</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SPIR-V] OpenCL CTS basic progvar_prog_scope_uninit, VReg's low-level type and register class have different sizes (OpConstantComposite)
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            backend:SPIR-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          michalpaszkowski
      </td>
    </tr>
</table>

<pre>
    ```
./test_basic progvar_prog_scope_uninit
 Initializing random seed to 0.
Requesting Default device based on command line for platform index 0 and device index 0
Compute Device Name = Intel(R) Graphics [0xa780], Compute Device Vendor = Intel(R) Corporation, Compute Device Version = OpenCL 3.0 NEO , CL C Version = OpenCL C 1.2 
Device latest conformance version passed: v2022-04-22-00
Supports single precision denormals: YES
sizeof( void*) = 8  (host)
sizeof( void*) = 8 (device)
progvar_prog_scope_uninit...
  bool OK
  uchar OK
 uchar2 OK
  uchar3 OK
  uchar4 OK
  uchar8 OK
  uchar16 OK
 char OK
  char2 OK
  char3 OK
  char4 OK
  char8 OK
  char16 OK
  ushort OK
  ushort2 OK
  ushort3 OK
  ushort4 OK
 ushort8 OK
  ushort16 OK
  short OK
  short2 OK
  short3 OK
 short4 OK
  short8 OK
  short16 OK
  uint OK
  uint2 OK
 uint3 OK
  uint4 OK
  uint8 OK
  uint16 OK
  int OK
  int2 OK
  int3 OK
  int4 OK
  int8 OK
  int16 OK
  ulong OK
LLVM ERROR: VReg's low-level type and register class have different sizes: %6:id(s32) = OpConstantComposite %2:type(s32), %17:id(p0), %17:id(p0) (in function: from_buf)
Aborted (core dumped)
```

Dump files from the failure:
```
-rw-rw-r-- 1 michalpaszkowski michalpaszkowski    896 2024-06-17 02:12:04.907139618 -0700 OCL_asm662b8d6e0d2d13cc.cl
-rw-rw-r-- 1 michalpaszkowski michalpaszkowski   5644 2024-06-17 02:12:04.907139618 -0700 OCL_asm662b8d6e0d2d13cc_1_compiler_input_.spv
-rw-rw-r-- 1 michalpaszkowski michalpaszkowski   8296 2024-06-17 02:12:04.915140325 -0700 OCL_asm662b8d6e0d2d13cc_2_spirv_backend_input_opaque.ll
-rw-rw-r-- 1 michalpaszkowski michalpaszkowski  19733 2024-06-17 02:12:04.915140325 -0700 OCL_asm662b8d6e0d2d13cc_2_spirv_backend_alternative_input_typed.ll
```

Dumps:
[test_basi_6341.zip](https://github.com/user-attachments/files/15864592/test_basi_6341.zip)

</pre>
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