<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/94964>94964</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [SPIR-V] Bad OpSwitch generation with i64 immediates
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            backend:SPIR-V
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          Keenuts
      </td>
    </tr>
</table>

<pre>
    When a 64-bit immediate value is used in a switch construct, the SPIR-V emitter splits the 64bit int into 2 32-bit integers, causing a bad instruction to be generated:

```
OpSwitch %5 %8 4294967295 4294967295 %9
instead of
OpSwitch %5 %8 -1 %9
```

Test case to reproduce:
```cpp
; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}

; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}

; CHECK-SPIRV:        %[[#cond:]] = OpFunctionParameter %[[#]]
; CHECK-SPIRV:                      OpSwitch %[[#cond]] %[[#default:]] -1 %[[#case_one:]]
; CHECK-SPIRV-DAG:  %[[#default]] = OpLabel
; CHECK-SPIRV-DAG: %[[#case_one]] = OpLabel

define spir_kernel void @bar(i64 %cond) {
entry:
  switch i64 %cond, label %default [ i64 -1, label %case_one ]
case_one:
  ret void
default:
  ret void
}
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzMVU2P2zYQ_TXUZcAFRX1YOuiwtuq2SNENkjY9BpQ0tpmlSYGkvN1_X5CSv9pNAuRUwaak4cx7b0iORjgn9xqxIcWaFG0iJn8wtnmHqCfvks4Mr81fB9QgoMxpJz3I4xEHKTzCSagJQTqYHA4gg497kb4_QG-083bqPeEb8AeEj-9__UA_AR6l92jBjUp6F2fKPILq-DfAIeN0seAerQsIvZic1HsQ0IlANGNLo8Eb6BD2qNEKjwPJHglrCTuPJVt-8fVp_DjLI7wowlBBzuu8Lle8Lm4fCS_qOSRwoRjA7L4KQdMb_38xzuMf6Dz0wmGQa3G0Zph6vGo9x_TjuFiyNXz483eSPYJSPdAnBvTorRwVkqx1o7SnMqeTftbmRZ_vQYUDaoACWW1gKxVuDtg_L3bahxc6WtzJv0nWbn75afOOhn359B9Swgu5g8hDvTHKBQtZrX9MDd1Jhf51DN6m-xLVzdgnoWbk9m7Xvp99xv9P2X9TzY9kf6sue4TlCr6hSNeEZ73R8bAXLSlaIFkLT-N20rEo3gsrjhjK7DZidv0ex_11e9rvqRfeG_OAOzEpfxU118U1TDj8bDReHN6UQtvHn6Oct6Bvk_1NdKi-CfEm-dcg4jjgTmqMu_P5Ga1GBScjByA564QlvJJlHmDjCvAayGo9B6L29vVSz3D-Ct65b0AFvmBY8gFSrKMPTe-mz2Lhski3a7dQWPRR3EX5efHfnL-esfO3JhmabKizWiTYpKu0YmlV50VyaFaiLHla9au6Lqo629U1E6yqdzyrqjRjXSIbznjOypSlKa8Ze-i7tBZduUqLknWrISM5w6OQ6kGp0_HB2H0inZuwCZ_XPIlputhuOO-mPeGc8E14Fv0zxlM9N4swUbSJbQIM7aa9IzlT0nl3BfbSq9i6lpCihbUYrud2aQyhU7xIP-_IpX-5ZLKqOXg_urBwfEv4di_9YeoeenMkfBtolhsdrfmCoZ9tYzKO8O2cz6nh_wQAAP__NIAYRg">