<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/94500>94500</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [RISCV] Vector Store/Load whole-register for multiple registers only has DWARF CFI for one register
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            bug,
            backend:RISC-V,
            debuginfo
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          ilovepi
      </td>
    </tr>
</table>

<pre>
    As seen in our tests (https://github.com/llvm/llvm-project/blob/0295c2ada4d9964a2b6289c905e320bd42461f99/llvm/test/CodeGen/RISCV/rvv-cfi-info.ll#L80C1-L84C8), when spilling vector registers to the stack, we only emit DWARF CFI directives for the register named in the store. Note, that in the code listing in the test, there are other `.cfi_directives`, but those are for other stores earlier in the function.

```asm
 vs4r.v v4, (a0) ;; Unknown-size Folded Spill
;; ...
.cfi_escape 0x10, 0x64, 0x0b, 0x11, 0x60, 0x22, 0x11, 0x78, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 ;; $v4m4 @ cfa - 32 - 8 * vlenb
```

This seems like an oversight in [createDefCFAOffset](https://github.com/llvm/llvm-project/blob/f4681be06b465736cc993b114dd8e2625d37b779/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp#L500), or maybe it's callers.

It may be worth considering extending the DWARF registers so that they can reference the register groups used w/ these instructions to keep the debug info compact.
</pre>
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