<table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Issue</th>
<td>
<a href=https://github.com/llvm/llvm-project/issues/94328>94328</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>
[VPlan] Report "Assertion `!State->VF.isScalable() && "VF is assumed to be non scalable."' failed"
</td>
</tr>
<tr>
<th>Labels</th>
<td>
new issue
</td>
</tr>
<tr>
<th>Assignees</th>
<td>
</td>
</tr>
<tr>
<th>Reporter</th>
<td>
eastB233
</td>
</tr>
</table>
<pre>
The IR is put at the end.
Compile command is `opt -passes=loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue`
The error is
```
opt: /root/llvm-project/llvm/lib/Transforms/Vectorize/VPlan.cpp:734: virtual void llvm::VPRegionBlock::execute(llvm::VPTransformState*): Assertion `!State->VF.isScalable() && "VF is assumed to be non scalable."' failed.
```
It can be seen at https://godbolt.org/z/s4bqzdKPP
```
; ModuleID = 'test.cpp'
source_filename = "test.cpp"
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"
%struct.ident_t = type { i32, i32, i32, i32, ptr }
@0 = private unnamed_addr constant [23 x i8] c";unknown;unknown;0;0;;\00", align 1
@1 = private unnamed_addr constant %struct.ident_t { i32 0, i32 514, i32 0, i32 22, ptr @0 }, align 8
@2 = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 22, ptr @0 }, align 8
; Function Attrs: mustprogress nounwind uwtable vscale_range(1,16)
define dso_local void @_Z4testiiPdS_(i32 noundef %nx, i32 noundef %ik, ptr noundef %out, ptr noundef %rspace) local_unnamed_addr #0 {
entry:
%nx.addr = alloca i32, align 4
%ik.addr = alloca i32, align 4
%out.addr = alloca ptr, align 8
%rspace.addr = alloca ptr, align 8
store i32 %nx, ptr %nx.addr, align 4
store i32 %ik, ptr %ik.addr, align 4
store ptr %out, ptr %out.addr, align 8
store ptr %rspace, ptr %rspace.addr, align 8
call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr nonnull @2, i32 4, ptr nonnull @_Z4testiiPdS_.omp_outlined, ptr nonnull %nx.addr, ptr nonnull %ik.addr, ptr nonnull %out.addr, ptr nonnull %rspace.addr)
ret void
}
; Function Attrs: alwaysinline norecurse nounwind uwtable vscale_range(1,16)
define internal void @_Z4testiiPdS_.omp_outlined(ptr noalias nocapture noundef readonly %.global_tid., ptr noalias nocapture noundef readnone %.bound_tid., ptr noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) %nx, ptr noalias nocapture noundef nonnull readonly align 4 dereferenceable(4) %ik, ptr noalias nocapture noundef nonnull readonly align 8 dereferenceable(8) %out, ptr noalias nocapture noundef nonnull readonly align 8 dereferenceable(8) %rspace) #1 {
entry:
%.omp.lb = alloca i64, align 8
%.omp.ub = alloca i64, align 8
%.omp.stride = alloca i64, align 8
%.omp.is_last = alloca i32, align 4
%0 = load i32, ptr %nx, align 4
%1 = load i32, ptr %ik, align 4
%cmp = icmp sgt i32 %0, 0
%cmp8 = icmp sgt i32 %1, 0
%or.cond = select i1 %cmp, i1 %cmp8, i1 false
br i1 %or.cond, label %omp.precond.then, label %omp.precond.end
omp.precond.then: ; preds = %entry
%conv = zext i32 %0 to i64
%conv6 = zext i32 %1 to i64
%mul = mul nuw nsw i64 %conv6, %conv
%sub7 = add nsw i64 %mul, -1
call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %.omp.lb) #3
store i64 0, ptr %.omp.lb, align 8
call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %.omp.ub) #3
store i64 %sub7, ptr %.omp.ub, align 8
call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %.omp.stride) #3
store i64 1, ptr %.omp.stride, align 8
call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %.omp.is_last) #3
store i32 0, ptr %.omp.is_last, align 4
%2 = load i32, ptr %.global_tid., align 4
call void @__kmpc_for_static_init_8(ptr nonnull @1, i32 %2, i32 33, ptr nonnull %.omp.is_last, ptr nonnull %.omp.lb, ptr nonnull %.omp.ub, ptr nonnull %.omp.stride, i64 1, i64 512)
%3 = load i64, ptr %.omp.ub, align 8
%cond60 = call i64 @llvm.smin.i64(i64 %3, i64 %sub7)
store i64 %cond60, ptr %.omp.ub, align 8
%4 = load i64, ptr %.omp.lb, align 8
%cmp12.not61 = icmp sgt i64 %4, %cond60
br i1 %cmp12.not61, label %omp.dispatch.end, label %omp.inner.for.cond.preheader.lr.ph
omp.inner.for.cond.preheader.lr.ph: ; preds = %omp.precond.then
br label %omp.inner.for.cond.preheader
omp.inner.for.cond.preheader: ; preds = %omp.inner.for.cond.preheader.lr.ph, %omp.dispatch.inc
%5 = phi i64 [ %4, %omp.inner.for.cond.preheader.lr.ph ], [ %add42, %omp.dispatch.inc ]
%cond62 = phi i64 [ %cond60, %omp.inner.for.cond.preheader.lr.ph ], [ %cond, %omp.dispatch.inc ]
%smax = call i64 @llvm.smax.i64(i64 %cond62, i64 %5)
%6 = add i64 %smax, 1
%7 = load ptr, ptr %rspace, align 8
%8 = load ptr, ptr %out, align 8
br label %omp.inner.for.body
omp.inner.for.body: ; preds = %omp.inner.for.cond.preheader, %omp.inner.for.body
%.omp.iv.059 = phi i64 [ %5, %omp.inner.for.cond.preheader ], [ %add41, %omp.inner.for.body ]
%div18 = sdiv i64 %.omp.iv.059, %conv6
%conv20 = trunc i64 %div18 to i32
%mul30 = mul nsw i64 %div18, %conv6
%sub31 = sub nsw i64 %.omp.iv.059, %mul30
%conv34 = trunc i64 %sub31 to i32
%mul35 = mul nsw i32 %1, %conv20
%add36 = add nsw i32 %mul35, %conv34
%idxprom = sext i32 %add36 to i64
%arrayidx = getelementptr inbounds double, ptr %7, i64 %idxprom
%9 = load double, ptr %arrayidx, align 8
%arrayidx40 = getelementptr inbounds double, ptr %8, i64 %idxprom
store double %9, ptr %arrayidx40, align 8
%add41 = add i64 %.omp.iv.059, 1
%exitcond = icmp ne i64 %add41, %6
br i1 %exitcond, label %omp.inner.for.body, label %omp.dispatch.inc
omp.dispatch.inc: ; preds = %omp.inner.for.body
%10 = load i64, ptr %.omp.stride, align 8
%add42 = add nsw i64 %10, %5
store i64 %add42, ptr %.omp.lb, align 8
%add43 = add nsw i64 %10, %cond62
%cond = call i64 @llvm.smin.i64(i64 %add43, i64 %sub7)
store i64 %cond, ptr %.omp.ub, align 8
%cmp12.not = icmp sgt i64 %add42, %cond
br i1 %cmp12.not, label %omp.dispatch.cond.omp.dispatch.end_crit_edge, label %omp.inner.for.cond.preheader
omp.dispatch.cond.omp.dispatch.end_crit_edge: ; preds = %omp.dispatch.inc
br label %omp.dispatch.end
omp.dispatch.end: ; preds = %omp.dispatch.cond.omp.dispatch.end_crit_edge, %omp.precond.then
call void @__kmpc_for_static_fini(ptr nonnull @1, i32 %2)
call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %.omp.is_last) #3
call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %.omp.stride) #3
call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %.omp.ub) #3
call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %.omp.lb) #3
br label %omp.precond.end
omp.precond.end: ; preds = %omp.dispatch.end, %entry
ret void
}
; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #2
; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #2
; Function Attrs: nounwind
declare void @__kmpc_for_static_init_8(ptr, i32, i32, ptr, ptr, ptr, ptr, i64, i64) local_unnamed_addr #3
; Function Attrs: nounwind
declare void @__kmpc_for_static_fini(ptr, i32) local_unnamed_addr #3
; Function Attrs: nounwind
declare void @__kmpc_fork_call(ptr, i32, ptr, ...) local_unnamed_addr #3
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.smin.i64(i64, i64) #4
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare i64 @llvm.smax.i64(i64, i64) #4
attributes #0 = { mustprogress nounwind uwtable vscale_range(1,16) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+v8a,-fmv" }
attributes #1 = { alwaysinline norecurse nounwind uwtable vscale_range(1,16) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+fullfp16,+neon,+sve,+v8a,-fmv" }
attributes #2 = { mustprogress nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }
attributes #4 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
```
</pre>
<img width="1px" height="1px" alt="" src="http://email.email.llvm.org/o/eJzsWstu4zrSfhpmQ0iQqIvtRRZJ_Ac4-DFAo_ugF7MxaKlsc0KRGpJykn76Aam7ZCVOOnNmFtPoWBJZVfxYrBslUq3ZUQDcouQeJdsbWpmTVLdAtbknUXSzl_nr7Z8nwH98x0zjsjKYGmxOgEHkPgq2KLirfx9kUTIOOJNFQUVuqVEayNJgr6Rag0bRlktZemfIjFTsF2CvVHAAZS85y6gBT55BeVAyLo8VoGjb9wDX4OmMcjogSIMhAgsTlJIKM920p0Hz3z3K0qDoDiPyqKQ0iDxyfi68Usl_QNY-2gvbI_L4p6JCH6QqNCKPP1vM9v4bp8LPyhJFd6sothLPTJmKcnyWLMdOSnSHoruf377DkUlxz2X2VDfBC2SVAUTWQ7JurB-G2s47RDZW7p3WoAyTwqoSkdB1eyj6v5-PPtM_rDb23ApDZIMRSRFJMSLk56PVPtW6KiDHRuI9YCEF1g2DjwhBZIUPlHHoVnGsq_r3D4MzKiy_BhB26U_GlNriJo-IPB5lvpfc-FIdEXn8hcijjvf__JX__7dvQzFT2dE9_pvMKw5_bDGKthiRlQFtnFLJqibSslIZ7A6Mg6AFNHSkpyM1naHqCAbn1FBOX2VlWkrwrH7BY2sU3dm_iHgsTFF0537sU2pXL409FhJLEJK1JyJSt_2wbZNBjGIl76BQqrJTGnuVeBLyWXicierFO4qqY2t-SaKNqjLjsxyE2dUIzWsJGK3uMYsIIg-XL6VRGK22I2lxEDgBpWJnagBXwuon39E8VziTQhsqDEbJPYnwC2ZrlGxxZiFF9w3S0V3Q_Nn_yUMQONt4wJSzo8BhN2Z4zZjzidbzw0EzJ5yEcXvbtZF-qm5uq20PYN0BIF8DgHxq-M5sHyuROYe8M0ZZP8BFpU2p5FGB1ljISjwzkePq2VhPw2frc7BTVBytn4aIPISp9W4nMYcDE4BzLXdcZm0AQXGw-3tsDZ2xb_mPHSJri9PKzuFgJyleWvCDRvbUzmPQKCtzoVXpkmZgg4YbdjfSJiKR1cJ9DRGEUa_W390Trkf3a8Joiym3ElpzrZUWN7QO03WkDdQZcWnUbDH6CVxHjrWRCpy2OtW51e5mcgHPiKfXbD-lRZ6GbKD4wdwW0TV07cI8jBsWeDPKW5Mh62bufeCwF9_3XWqIg93uqSiz3UGqp53lqzlsWhAV55ai84y4t5iuc2SQvizKnawMZwLyGfFIrZOegfImPUMNTbpGOti0elNg3Nwb35wEyYuuSvkzfdVMWNxYSAVZpTR80mmZMKDEks9OVNTomnJGbZDIaGkqBZ1LKqC5FPzVztY_crmnfGdY7vfKeItTSAGOc28br2Rs9dsN3RgzzsEVZSAyaIqLuK4uBq7zpWKHceuDYtcXxDa10DjyfaHcPnYiEoVvBkprBD7fj6JfGl-IAS1t9QFabRTL4Xp6pnecanNVKK4LDC5pPipEWhOYM4RLDPXizhmyonQszN7oo2lDrcvKwZhwfZEynFJK5WdS5I5YA4fMYBY2Ilxoax_WzdOBcg2tgL1qCBoxlobTPdTBqSj9UoFt980JxGIniHwYhmZ8dvcR3WO7rdFNGZnUhjOYsRRn1_cLXnq92DLeLvCYLp0RhnPCouKOzF5F9YyFfrYUnQw7m-Z-wKWr_ao2ljwfshQVtwxe2NIOslAc2F2Nz9kBDCvA14Yq45eBrWDSGK8vBPfGRxp_iib5N43rOq2xpo54ZuVfAKJ6A0SjjymU6t8EpfbtZTjhFEjL8Btg5ll_HDgW0LSV9BBNx3GhIiRLkWKa9yYxYzSRvpjZaUMNy3ZMMLNbz4uasC1q7NDtfRS9O9dlO102nrfX8qFfOXuThGRQzCCSRAPFpPE1llb7bJ7W0dopyNlqs9C6YMJ3otaNCUft4J05by6aei31KmNHJInfBH7JW-swHBJfSJOGk-heQ4j7oJSnwSxID9hnsThnuqQmO7lgPO1kQoDyD02Qt8H5BDQH5XPll6dp7H6H-lI0n4X8HvpVQK6FsDj4O5hrtY70xETWL0xSb7NPrF6J5H64Gu_Lxyhx2-eGkeZ5TBbGdKSjdJan5NLovTl-BkKbzN9GYD2ioC9LnkRfxp5Ugx24UzJ25rTLnK27FdSVTuGAaNU7TrNdm-0C5962XmJq6t0Jx7LZ7WX-umxsrvejJnZxifpxBrXo2Q-SzaW1Tq5Y5gs2Fi4OPbGynJ3DWoU6Z-d2dQagBsVQOim2SB1ojapE1nLW8mzJFZHelIqKR0Ffc_XFkyNfGEJX-6gOhrraD5nm6Jz8CboonqOrRY7QtezJGN6gpu5mO-CgeR6l42qw5nCiBlzRsPBk-UupZNFU5H2NWkub1alUKfrK8toJj2CAQwHCWPtmwu1tNc5l5bZjndmvBk7YjDcQuem9ZcbZDnfZz9reOPgQnPUynDrF1hwO2wUscbCAxtr4NKZM7GIYWuCFmW4z5HKr6LL70F_SWWZtOd_InM6jF7Nul036sDLqi-7we__eCTqTiBIGbxYgi6Vxm54ubXLCNt0kFwukLq29uy9piKM3B2myyTgXXlvUOfEfKOyuLeu6EutifTZM7E7qYoW2bCkuqk8rtl2mmNlBfoSra7dFc3tvgKX8dqEymiXSUZW5BMD2fdbeP6Km5brznW3TgQn27qZpc8VmEuyCfHYrea3cD-6Xf1vs_I3Ab4ucv-mYGtYVr5KuNKt37Aq6unj0BuoT79Unn8CskvY0e8JCHhQAFlK_iqx_zf7MOFdgKiVwAYVUr4isqToWUFhhCmj-rJiBwQv3jFMF173GYEVB1bFXf_PGt9E6-S-fzMiIfnsqLcjLI7_9EgVd-ha9eGnyrrssfVSMvh5wH746nH_B6MMPaIuf3H4DxXsmp0vIKk7rb1WX7E9IMTe45SpisHKItAX8fx7icM_9BkRqjGL7yoBuvlzbULe6_-R3eYwIOShagFdK94XPHZzYIkKEFB4HekDE5kUipGcULUsmjl5BzamjM6qChkYbmj15pZLGHR_y9tXhAMrT7hxRQ75uaOsTJl5WVl3XEQQolo0JDkBtENAdFSL3h9KjqjjbpGOfKs4PpZ2NfRIgRX2nz1DfnNcUkQfvUJyd6DbCjxUZdor83a-m_1Npo1KyZJtfl2OWho66oTuhC5TxgPKrvHx2hKk9DnaT30b5JtrQG7gNV-Eq3pBkvbk53VKy2icJ5IeAHiA5kDANV6vVHmK6DpKc0Bt2SwISB2kQB5swJRt_lR_iPWRpvCH7zT6KURxAQRn3XTSR6njDtK7gdhNHZH3jKi7tDj0SIuAZu0679Mn2Rt26c4H76qhtNGLa6F6KYYa705LuGCBKtvg7lFIZa09_yXE9RMhNpfjt5CAeM6dq72eyGJxjHJ9udFPUiDzWKjjfkn8FAAD__yr8rgQ">