<table border="1" cellspacing="0" cellpadding="8">
    <tr>
        <th>Issue</th>
        <td>
            <a href=https://github.com/llvm/llvm-project/issues/94344>94344</a>
        </td>
    </tr>

    <tr>
        <th>Summary</th>
        <td>
            [DAG] computeKnownBits - ISD::ABS is zero in the high bits if the input has multiple sign bits
        </td>
    </tr>

    <tr>
      <th>Labels</th>
      <td>
            llvm:SelectionDAG
      </td>
    </tr>

    <tr>
      <th>Assignees</th>
      <td>
      </td>
    </tr>

    <tr>
      <th>Reporter</th>
      <td>
          RKSimon
      </td>
    </tr>
</table>

<pre>
    Alive2: https://alive2.llvm.org/ce/z/a87fHU

If the absolute value input is sign extended, then the absolute result is guaranteed to be zero in the (NumSignBits - 1) upper bits.

ISD::ABDS should be similar as well.

Noticed while working on #92576
</pre>
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